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Re: [PATCH v2 12/12] target/arm: Allow users to set the number of VFP re
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v2 12/12] target/arm: Allow users to set the number of VFP registers |
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Date: |
Thu, 8 Jun 2023 11:19:22 +0100 |
On Wed, 7 Jun 2023 at 05:40, Cédric Le Goater <clg@kaod.org> wrote:
>
> Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
> have 16 64-bit FPU registers and not 32 registers. Let users set the
> number of VFP registers with a CPU property.
>
> The primary use case of this property is for the Cortex A7 of the
> Aspeed AST2600 SoC.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v2 09/12] m25p80: Introduce an helper to retrieve the BlockBackend of a device, (continued)
- [PATCH v2 09/12] m25p80: Introduce an helper to retrieve the BlockBackend of a device, Cédric Le Goater, 2023/06/07
- [PATCH v2 11/12] aspeed: Introduce a "bmc-console" machine option, Cédric Le Goater, 2023/06/07
- [PATCH v2 08/12] aspeed: Create flash devices only when defaults are enabled, Cédric Le Goater, 2023/06/07
- [PATCH v2 10/12] aspeed: Get the BlockBackend of FMC0 from the flash device, Cédric Le Goater, 2023/06/07
- [PATCH v2 12/12] target/arm: Allow users to set the number of VFP registers, Cédric Le Goater, 2023/06/07