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[PATCH 05/33] target/mips: Add emulation of Q8SLT Q8SLTU instructions
From: |
Siarhei Volkau |
Subject: |
[PATCH 05/33] target/mips: Add emulation of Q8SLT Q8SLTU instructions |
Date: |
Thu, 8 Jun 2023 13:41:54 +0300 |
These instructions are used to set bits depending on
comparison result in each byte respectively.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
target/mips/tcg/mxu_translate.c | 65 +++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index f2c932eeb7..b7bdc07dd7 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -389,6 +389,8 @@ enum {
OPC_MXU_D16MIN = 0x03,
OPC_MXU_Q8MAX = 0x04,
OPC_MXU_Q8MIN = 0x05,
+ OPC_MXU_Q8SLT = 0x06,
+ OPC_MXU_Q8SLTU = 0x07,
};
/*
@@ -1399,6 +1401,63 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
}
}
+/*
+ * Q8SLT
+ * Update XRa with the signed "set less than" comparison of XRb and XRc
+ * on per-byte basis.
+ * a.k.a. XRa[0..3] = XRb[0..3] < XRc[0..3] ? 1 : 0;
+ *
+ * Q8SLTU
+ * Update XRa with the unsigned "set less than" comparison of XRb and XRc
+ * on per-byte basis.
+ * a.k.a. XRa[0..3] = XRb[0..3] < XRc[0..3] ? 1 : 0;
+ */
+static void gen_mxu_q8slt(DisasContext *ctx, bool sltu)
+{
+ uint32_t pad, XRc, XRb, XRa;
+
+ pad = extract32(ctx->opcode, 21, 5);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+
+ if (unlikely(pad != 0)) {
+ /* opcode padding incorrect -> do nothing */
+ } else if (unlikely(XRa == 0)) {
+ /* destination is zero register -> do nothing */
+ } else if (unlikely((XRb == 0) && (XRc == 0))) {
+ /* both operands zero registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else if (unlikely(XRb == XRc)) {
+ /* both operands same registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else {
+ /* the most general case */
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+ TCGv t4 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t3, XRb);
+ gen_load_mxu_gpr(t4, XRc);
+ tcg_gen_movi_tl(t2, 0);
+
+ for (int i = 0; i < 4; i++) {
+ if (sltu) {
+ tcg_gen_extract_tl(t0, t3, 8 * i, 8);
+ tcg_gen_extract_tl(t1, t4, 8 * i, 8);
+ } else {
+ tcg_gen_sextract_tl(t0, t3, 8 * i, 8);
+ tcg_gen_sextract_tl(t1, t4, 8 * i, 8);
+ }
+ tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
+ tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
+ }
+ gen_store_mxu_gpr(t2, XRa);
+ }
+}
+
/*
* MXU instruction category: align
@@ -1664,6 +1723,12 @@ static void decode_opc_mxu__pool00(DisasContext *ctx)
case OPC_MXU_Q8MIN:
gen_mxu_Q8MAX_Q8MIN(ctx);
break;
+ case OPC_MXU_Q8SLT:
+ gen_mxu_q8slt(ctx, false);
+ break;
+ case OPC_MXU_Q8SLTU:
+ gen_mxu_q8slt(ctx, true);
+ break;
default:
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
--
2.40.0
- [PATCH 00/33] target/mips: Finalise the Ingenic MXU ASE support, Siarhei Volkau, 2023/06/08
- [PATCH 03/33] target/mips: Add emulation of LXW LXB LXH LXBU LXHU instructions, Siarhei Volkau, 2023/06/08
- [PATCH 12/33] target/mips: Add emulation of MXU D16MADL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 15/33] target/mips: Add emulation of MXU D32ADD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 04/33] target/mips: Add emulation of S32MADD/MADDU/MSUB/MSUBU instructions, Siarhei Volkau, 2023/06/08
- [PATCH 05/33] target/mips: Add emulation of Q8SLT Q8SLTU instructions,
Siarhei Volkau <=
- [PATCH 06/33] target/mips: fix MXU D16MAX D16MIN Q8MAX Q8MIN instructions, Siarhei Volkau, 2023/06/08
- [PATCH 11/33] target/mips: Add emulation of MXU D16MACF D16MACE instructions, Siarhei Volkau, 2023/06/08
- [PATCH 02/33] Add support of two XBurst CPUs, Siarhei Volkau, 2023/06/08
- [PATCH 01/33] target/mips: Add emulation of MXU instructions for 32-bit load/store, Siarhei Volkau, 2023/06/08
- [PATCH 07/33] target/mips: Add emulation of MXU S32SLT D16SLT D16AVG[R] Q8AVG[R] insns, Siarhei Volkau, 2023/06/08
- [PATCH 13/33] target/mips: Add emulation of MXU S16MAD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 16/33] target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions, Siarhei Volkau, 2023/06/08
- [PATCH 18/33] target/mips: Add emulation of MXU Q16ACC Q16ACCM D16ASUM instructions, Siarhei Volkau, 2023/06/08
- [PATCH 19/33] target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC instructions, Siarhei Volkau, 2023/06/08
- [PATCH 22/33] target/mips: Add emulation of MXU S32MUL S32MULU S32EXTR S32EXTRV insns, Siarhei Volkau, 2023/06/08