Re: [PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value

[Alistair Francis]

On Tue, May 30, 2023 at 11:22 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The enum value 'rv_op_illegal' does not represent an
> instruction, but is a catch-all value in case we have
> no match in the decoder. Let's make the value a shared
> one, so that other compile units can reuse it.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  disas/riscv.c | 2 +-
>  disas/riscv.h | 4 ++++
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index a062fb48cc..4cf477bc02 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -22,7 +22,7 @@
>  #include "disas/riscv.h"
>
>  typedef enum {
> -    rv_op_illegal = 0,
> +    /* 0 is reserved for rv_op_illegal. */
>      rv_op_lui = 1,
>      rv_op_auipc = 2,
>      rv_op_jal = 3,
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 0f34b71518..de2623e3cc 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -189,6 +189,10 @@ typedef struct {
>      const rvc_constraint *constraints;
>  } rv_comp_data;
>
> +enum {
> +    rv_op_illegal = 0
> +};
> +
>  enum {
>      rvcd_imm_nz = 0x1
>  };
> --
> 2.40.1
>
>