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Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler
From: |
Christoph Müllner |
Subject: |
Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler |
Date: |
Mon, 12 Jun 2023 11:47:40 +0200 |
On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei <baxiantai@gmail.com> wrote:
>
>
> On 2023/5/30 21:18, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > The disassembler needs the available extensions in order
> > to properly decode instructions in case of overlapping
> > encodings (e.g. for vendor extensions).
> >
> > Let's use the field 'disassemble_info::private_data' to store
> > our RISCVCPUConfig pointer.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> > target/riscv/cpu.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 5b7818dbd1..6f0cd9a0bb 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -819,6 +819,9 @@ static void riscv_cpu_disas_set_info(CPUState *s,
> > disassemble_info *info)
> > {
> > RISCVCPU *cpu = RISCV_CPU(s);
> > CPURISCVState *env = &cpu->env;
> > + RISCVCPUConfig *cfg = &cpu->cfg;
> > +
> > + info->private_data = cfg;
>
> I don't know if this field will be overridden by the binutils. Can we
> extend the struct disassemble_info, and add some fields like supporting
> for Capstone?
Initially I wanted to add a new field, but then I noticed that the field
'disassemble_info::private_data' is used for a similar purpose by
disas/cris.c, disas/m68k.c, and dias/xtensa.c.
So I decided to not add yet another field, which only serves one architecture.
But if that's the preferred way, then I can change.
Thanks
Christoph
>
> Zhiwei
>
> >
> > switch (env->xl) {
> > case MXL_RV32: