Re: [PATCH v2 14/23] target/arm: Convert load/store-pair to decodetree

[Richard Henderson]

On 6/11/23 18:00, Peter Maydell wrote:
> Convert the load/store register pair insns (LDP, STP,
> LDNP, STNP, LDPSW, STGP) to decodetree.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> Message-id:20230602155223.2040685-12-peter.maydell@linaro.org
> ---
> This was reviewed in v1, but the underlying code
> changed enough in the atomic-ops work that I've dropped
> the R-by tag.
> ---
>   target/arm/tcg/a64.decode      |  61 +++++
>   target/arm/tcg/translate-a64.c | 425 ++++++++++++++++-----------------
>   2 files changed, 271 insertions(+), 215 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


> +static bool trans_STP(DisasContext *s, arg_ldstpair *a)
> +{
> +    uint64_t offset = a->imm << a->sz;
> +    TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2;
> +    MemOp mop = finalize_memop(s, a->sz);
> +
> +    op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop);
> +    tcg_rt = cpu_reg(s, a->rt);
> +    tcg_rt2 = cpu_reg(s, a->rt2);
> +    /*
> +     * We built mop above for the single logical access -- rebuild it
> +     * now for the paired operation.
> +     *
> +     * With LSE2, non-sign-extending pairs are treated atomically if
> +     * aligned, and if unaligned one of the pair will be completely
> +     * within a 16-byte block and that element will be atomic.
> +     * Otherwise each element is separately atomic.
> +     * In all cases, issue one operation with the correct atomicity.
> +     *
> +     * This treats sign-extending loads like zero-extending loads,
> +     * since that reuses the most code below.
> +     */

Could lose the bit about loads within the store function.


r~