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[PULL 03/33] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_im
From: |
Peter Maydell |
Subject: |
[PULL 03/33] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode |
Date: |
Mon, 19 Jun 2023 15:28:44 +0100 |
In disas_ldst_reg_imm9() we missed one place where a call to
a gen_mte_check* function should now be passed the memop we
have created rather than just being passed the size. Fix this.
Fixes: 0a9091424d ("target/arm: Pass memop to gen_mte_check1*")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/tcg/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4ec857bcd8d..d271449431a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -3226,7 +3226,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn,
clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store,
writeback || rn != 31,
- size, is_unpriv, memidx);
+ memop, is_unpriv, memidx);
if (is_vector) {
if (is_store) {
--
2.34.1
- [PULL 00/33] target-arm queue, Peter Maydell, 2023/06/19
- [PULL 01/33] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics, Peter Maydell, 2023/06/19
- [PULL 02/33] target/arm: Return correct result for LDG when ATA=0, Peter Maydell, 2023/06/19
- [PULL 03/33] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode,
Peter Maydell <=
- [PULL 04/33] target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores, Peter Maydell, 2023/06/19
- [PULL 06/33] target/arm: Convert barrier insns to decodetree, Peter Maydell, 2023/06/19
- [PULL 07/33] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree, Peter Maydell, 2023/06/19
- [PULL 12/33] target/arm: Convert LDXP, STXP, CASP, CAS to decodetree, Peter Maydell, 2023/06/19
- [PULL 13/33] target/arm: Convert load reg (literal) group to decodetree, Peter Maydell, 2023/06/19
- [PULL 05/33] target/arm: Convert hint instruction space to decodetree, Peter Maydell, 2023/06/19
- [PULL 09/33] target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree, Peter Maydell, 2023/06/19
- [PULL 11/33] target/arm: Convert load/store exclusive and ordered to decodetree, Peter Maydell, 2023/06/19
- [PULL 10/33] target/arm: Convert exception generation instructions to decodetree, Peter Maydell, 2023/06/19
- [PULL 08/33] target/arm: Convert MSR (immediate) to decodetree, Peter Maydell, 2023/06/19