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[PATCH v1 23/46] target/loognarch: Implement xvldi
From: |
Song Gao |
Subject: |
[PATCH v1 23/46] target/loognarch: Implement xvldi |
Date: |
Tue, 20 Jun 2023 17:37:51 +0800 |
This patch includes:
- XVLDI.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 7 +++++++
target/loongarch/insn_trans/trans_lasx.c.inc | 21 ++++++++++++++++++++
target/loongarch/insns.decode | 5 ++++-
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5a3c14f33d..82a9826eb7 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1703,6 +1703,11 @@ static bool trans_##insn(DisasContext *ctx, arg_##type *
a) \
return true; \
}
+static void output_x_i(DisasContext *ctx, arg_x_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "x%d, 0x%x", a->xd, a->imm);
+}
+
static void output_xxx(DisasContext *ctx, arg_xxx * a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, x%d", a->xd, a->xj, a->xk);
@@ -2021,6 +2026,8 @@ INSN_LASX(xvmskltz_d, xx)
INSN_LASX(xvmskgez_b, xx)
INSN_LASX(xvmsknz_b, xx)
+INSN_LASX(xvldi, x_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index b0aad21a9d..bf277e1fd9 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1914,6 +1914,27 @@ TRANS(xvmskltz_d, gen_xx, gen_helper_xvmskltz_d)
TRANS(xvmskgez_b, gen_xx, gen_helper_xvmskgez_b)
TRANS(xvmsknz_b, gen_xx, gen_helper_xvmsknz_b)
+static bool trans_xvldi(DisasContext *ctx, arg_xvldi * a)
+{
+ int sel, vece;
+ uint64_t value;
+ CHECK_ASXE;
+
+ sel = (a->imm >> 12) & 0x1;
+
+ if (sel) {
+ value = vldi_get_value(ctx, a->imm);
+ vece = MO_64;
+ } else {
+ value = ((int32_t)(a->imm << 22)) >> 22;
+ vece = (a->imm >> 10) & 0x3;
+ }
+
+ tcg_gen_gvec_dup_i64(vece, vec_full_offset(a->xd), 32, ctx->vl / 8,
+ tcg_constant_i64(value));
+ return true;
+}
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index b792a68fdf..fbd0dd229a 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1305,11 +1305,13 @@ vstelm_b 0011 000110 .... ........ ..... .....
@vr_i8i4
&xxx xd xj xk
&xr xd rj
&xx_i xd xj imm
+&x_i xd imm
#
# LASX Formats
#
+@x_i13 .... ........ .. imm:13 xd:5 &x_i
@xx .... ........ ..... ..... xj:5 xd:5 &xx
@xxx .... ........ ..... xk:5 xj:5 xd:5 &xxx
@xr .... ........ ..... ..... rj:5 xd:5 &xr
@@ -1319,7 +1321,6 @@ vstelm_b 0011 000110 .... ........ ..... .....
@vr_i8i4
@xx_ui5 .... ........ ..... imm:5 xj:5 xd:5 &xx_i
@xx_ui6 .... ........ .... imm:6 xj:5 xd:5 &xx_i
-
xvadd_b 0111 01000000 10100 ..... ..... ..... @xxx
xvadd_h 0111 01000000 10101 ..... ..... ..... @xxx
xvadd_w 0111 01000000 10110 ..... ..... ..... @xxx
@@ -1625,6 +1626,8 @@ xvmskltz_d 0111 01101001 11000 10011 ..... .....
@xx
xvmskgez_b 0111 01101001 11000 10100 ..... ..... @xx
xvmsknz_b 0111 01101001 11000 11000 ..... ..... @xx
+xvldi 0111 01111110 00 ............. ..... @x_i13
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @xr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @xr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @xr
--
2.39.1
- [PATCH v1 08/46] target/loongarch: Implement xvsadd/xvssub, (continued)
- [PATCH v1 08/46] target/loongarch: Implement xvsadd/xvssub, Song Gao, 2023/06/20
- [PATCH v1 10/46] target/loongarch: Implement xvaddw/xvsubw, Song Gao, 2023/06/20
- [PATCH v1 12/46] target/loongarch: Implement xvabsd, Song Gao, 2023/06/20
- [PATCH v1 13/46] target/loongarch: Implement xvadda, Song Gao, 2023/06/20
- [PATCH v1 17/46] target/loongarch; Implement xvdiv/xvmod, Song Gao, 2023/06/20
- [PATCH v1 15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}, Song Gao, 2023/06/20
- [PATCH v1 19/46] target/loongarch: Implement xvexth, Song Gao, 2023/06/20
- [PATCH v1 18/46] target/loongarch: Implement xvsat, Song Gao, 2023/06/20
- [PATCH v1 21/46] target/loongarch: Implement xvsigncov, Song Gao, 2023/06/20
- [PATCH v1 20/46] target/loongarch: Implement vext2xv, Song Gao, 2023/06/20
- [PATCH v1 23/46] target/loognarch: Implement xvldi,
Song Gao <=
- [PATCH v1 22/46] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz, Song Gao, 2023/06/20
- [PATCH v1 24/46] target/loongarch: Implement LASX logic instructions, Song Gao, 2023/06/20
- [PATCH v1 26/46] target/loongarch: Implement xvsllwil xvextl, Song Gao, 2023/06/20
- [PATCH v1 25/46] target/loongarch: Implement xvsll xvsrl xvsra xvrotr, Song Gao, 2023/06/20
- [PATCH v1 27/46] target/loongarch: Implement xvsrlr xvsrar, Song Gao, 2023/06/20
- [PATCH v1 35/46] target/loongarch: Implement xvfrstp, Song Gao, 2023/06/20
- [PATCH v1 29/46] target/loongarch: Implement xvsrlrn xvsrarn, Song Gao, 2023/06/20
- [PATCH v1 31/46] target/loongarch: Implement xvssrlrn xvssrarn, Song Gao, 2023/06/20
- [PATCH v1 34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev, Song Gao, 2023/06/20
- [PATCH v1 36/46] target/loongarch: Implement LASX fpu arith instructions, Song Gao, 2023/06/20