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[PATCH v1 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr
From: |
Song Gao |
Subject: |
[PATCH v1 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr |
Date: |
Tue, 20 Jun 2023 17:38:09 +0800 |
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 17 ++++++
target/loongarch/insn_trans/trans_lasx.c.inc | 54 ++++++++++++++++++++
target/loongarch/insns.decode | 13 +++++
3 files changed, 84 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 5c2a81ee80..fd7d459921 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1738,6 +1738,16 @@ static void output_xr(DisasContext *ctx, arg_xr *a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, r%d", a->xd, a->rj);
}
+static void output_xr_i(DisasContext *ctx, arg_xr_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "x%d, r%d, 0x%x", a->xd, a->rj, a->imm);
+}
+
+static void output_rx_i(DisasContext *ctx, arg_rx_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, x%d, 0x%x", a->rd, a->xj, a->imm);
+}
+
INSN_LASX(xvadd_b, xxx)
INSN_LASX(xvadd_h, xxx)
INSN_LASX(xvadd_w, xxx)
@@ -2497,6 +2507,13 @@ INSN_LASX(xvsetallnez_h, cx)
INSN_LASX(xvsetallnez_w, cx)
INSN_LASX(xvsetallnez_d, cx)
+INSN_LASX(xvinsgr2vr_w, xr_i)
+INSN_LASX(xvinsgr2vr_d, xr_i)
+INSN_LASX(xvpickve2gr_w, rx_i)
+INSN_LASX(xvpickve2gr_d, rx_i)
+INSN_LASX(xvpickve2gr_wu, rx_i)
+INSN_LASX(xvpickve2gr_du, rx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index cefb6a4973..0fc26023d1 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -2782,6 +2782,60 @@ TRANS(xvsetallnez_h, gen_cx, gen_helper_xvsetallnez_h)
TRANS(xvsetallnez_w, gen_cx, gen_helper_xvsetallnez_w)
TRANS(xvsetallnez_d, gen_cx, gen_helper_xvsetallnez_d)
+static bool trans_xvinsgr2vr_w(DisasContext *ctx, arg_xr_i *a)
+{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+ CHECK_ASXE;
+ tcg_gen_st32_i64(src, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xd].xreg.XW(a->imm)));
+ return true;
+}
+
+static bool trans_xvinsgr2vr_d(DisasContext *ctx, arg_xr_i *a)
+{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+ CHECK_ASXE;
+ tcg_gen_st_i64(src, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xd].xreg.XD(a->imm)));
+ return true;
+}
+
+static bool trans_xvpickve2gr_w(DisasContext *ctx, arg_rx_i *a)
+{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+ CHECK_ASXE;
+ tcg_gen_ld32s_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XW(a->imm)));
+ return true;
+}
+
+static bool trans_xvpickve2gr_d(DisasContext *ctx, arg_rx_i *a)
+{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+ CHECK_ASXE;
+ tcg_gen_ld_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XD(a->imm)));
+ return true;
+}
+
+static bool trans_xvpickve2gr_wu(DisasContext *ctx, arg_rx_i *a)
+{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+ CHECK_ASXE;
+ tcg_gen_ld32u_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XW(a->imm)));
+ return true;
+}
+
+static bool trans_xvpickve2gr_du(DisasContext *ctx, arg_rx_i *a)
+{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+ CHECK_ASXE;
+ tcg_gen_ld_i64(dst, cpu_env,
+ offsetof(CPULoongArchState, fpr[a->xj].xreg.XD(a->imm)));
+ return true;
+}
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index b696d99577..8c87b3f840 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1309,6 +1309,8 @@ vstelm_b 0011 000110 .... ........ ..... .....
@vr_i8i4
&xxxx xd xj xk xa
&xxx_fcond xd xj xk fcond
&cx cd xj
+&xr_i xd rj imm
+&rx_i rd xj imm
#
# LASX Formats
@@ -1328,6 +1330,10 @@ vstelm_b 0011 000110 .... ........ ..... .....
@vr_i8i4
@xxxx .... ........ xa:5 xk:5 xj:5 xd:5 &xxxx
@xxx_fcond .... ........ fcond:5 xk:5 xj:5 xd:5 &xxx_fcond
@cx .... ........ ..... ..... xj:5 .. cd:3 &cx
+@xr_ui3 .... ........ ..... .. imm:3 rj:5 xd:5 &xr_i
+@xr_ui2 .... ........ ..... ... imm:2 rj:5 xd:5 &xr_i
+@rx_ui3 .... ........ ..... .. imm:3 xj:5 rd:5 &rx_i
+@rx_ui2 .... ........ ..... ... imm:2 xj:5 rd:5 &rx_i
xvadd_b 0111 01000000 10100 ..... ..... ..... @xxx
xvadd_h 0111 01000000 10101 ..... ..... ..... @xxx
@@ -2005,6 +2011,13 @@ xvsetallnez_h 0111 01101001 11001 01101 ..... 00 ...
@cx
xvsetallnez_w 0111 01101001 11001 01110 ..... 00 ... @cx
xvsetallnez_d 0111 01101001 11001 01111 ..... 00 ... @cx
+xvinsgr2vr_w 0111 01101110 10111 10 ... ..... ..... @xr_ui3
+xvinsgr2vr_d 0111 01101110 10111 110 .. ..... ..... @xr_ui2
+xvpickve2gr_w 0111 01101110 11111 10 ... ..... ..... @rx_ui3
+xvpickve2gr_d 0111 01101110 11111 110 .. ..... ..... @rx_ui2
+xvpickve2gr_wu 0111 01101111 00111 10 ... ..... ..... @rx_ui3
+xvpickve2gr_du 0111 01101111 00111 110 .. ..... ..... @rx_ui2
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @xr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @xr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @xr
--
2.39.1
- [PATCH v1 27/46] target/loongarch: Implement xvsrlr xvsrar, (continued)
- [PATCH v1 27/46] target/loongarch: Implement xvsrlr xvsrar, Song Gao, 2023/06/20
- [PATCH v1 35/46] target/loongarch: Implement xvfrstp, Song Gao, 2023/06/20
- [PATCH v1 29/46] target/loongarch: Implement xvsrlrn xvsrarn, Song Gao, 2023/06/20
- [PATCH v1 31/46] target/loongarch: Implement xvssrlrn xvssrarn, Song Gao, 2023/06/20
- [PATCH v1 34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev, Song Gao, 2023/06/20
- [PATCH v1 36/46] target/loongarch: Implement LASX fpu arith instructions, Song Gao, 2023/06/20
- [PATCH v1 37/46] target/loongarch: Implement LASX fpu fcvt instructions, Song Gao, 2023/06/20
- [PATCH v1 39/46] target/loongarch: Implement xvfcmp, Song Gao, 2023/06/20
- [PATCH v1 40/46] target/loongarch: Implement xvbitsel xvset, Song Gao, 2023/06/20
- [PATCH v1 43/46] target/loongarch: Implement xvpack xvpick xvilv{l/h}, Song Gao, 2023/06/20
- [PATCH v1 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr,
Song Gao <=
- [PATCH v1 42/46] target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v, Song Gao, 2023/06/20
- [PATCH v1 46/46] target/loongarch: CPUCFG support LASX, Song Gao, 2023/06/20
- [PATCH v1 45/46] target/loongarch: Implement xvld xvst, Song Gao, 2023/06/20
- [PATCH v1 38/46] target/loongarch: Implement xvseq xvsle xvslt, Song Gao, 2023/06/20
- [PATCH v1 30/46] target/loongarch: Implement xvssrln xvssran, Song Gao, 2023/06/20
- [PATCH v1 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}, Song Gao, 2023/06/20
- [PATCH v1 33/46] target/loongarch: Implement xvpcnt, Song Gao, 2023/06/20
- [PATCH v1 14/46] target/loongarch: Implement xvmax/xvmin, Song Gao, 2023/06/20
- [PATCH v1 44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins, Song Gao, 2023/06/20
- [PATCH v1 28/46] target/loongarch: Implement xvsrln xvsran, Song Gao, 2023/06/20