qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 8/8] target/tricore: Fix ICR.IE offset in RESTORE insn


From: Bastian Koppelmann
Subject: Re: [PATCH v3 8/8] target/tricore: Fix ICR.IE offset in RESTORE insn
Date: Wed, 21 Jun 2023 16:19:49 +0200

On Wed, Jun 21, 2023 at 01:06:33PM +0200, Richard Henderson wrote:
> On 6/21/23 12:19, Bastian Koppelmann wrote:
> > from ISA v1.6.1 onwards the bit position of ICR.IE changed.
> > ctx->icr_ie_offset contains the correct value for the ISA version used
> > by the vCPU.
> > 
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> > ---
> >   target/tricore/translate.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> > index 71b6209af4..9cab0734dd 100644
> > --- a/target/tricore/translate.c
> > +++ b/target/tricore/translate.c
> > @@ -7956,7 +7956,8 @@ static void decode_sys_interrupts(DisasContext *ctx)
> >       case OPC2_32_SYS_RESTORE:
> >           if (has_feature(ctx, TRICORE_FEATURE_16)) {
> >               if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == 
> > TRICORE_PRIV_UM1) {
> > -                tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
> > +                tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1],
> > +                        ctx->icr_ie_offset, 1);
> >               } else {
> >                   generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
> >               }
> 
> Need to exit the tb, like for ENABLE.

Thank you, for the thorough review. Will do.

Cheers,
Bastian



reply via email to

[Prev in Thread] Current Thread [Next in Thread]