Re: [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.

[Alistair Francis]

On Mon, Jun 19, 2023 at 7:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 12 Jun 2023 at 05:12, Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Fri, Jun 9, 2023 at 4:01 PM Tommy Wu <tommy.wu@sifive.com> wrote:
> > >
> > > According to the `The RISC-V Advanced Interrupt Architecture`
> > > document, if register `mmsiaddrcfgh` of the domain has bit L set
> > > to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
> > > read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
> > >
> > > Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> > > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> >
> > Thanks!
> >
> > Applied to riscv-to-apply.next
>
> If it hasn't gone in already, would you mind tweaking the
> subject line so that it says which interrupt controller
> the change is for ? (ie "hw/intc/riscv_aplic", not just "hw/intc".)

Sorry Peter, it's already in. I'll try to keep a closer eye on the
commit titles in future

Alistair

>
> thanks
> -- PMM