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[PATCH v4 17/17] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties
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From: |
Max Chou |
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Subject: |
[PATCH v4 17/17] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties |
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Date: |
Fri, 23 Jun 2023 00:16:33 +0800 |
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Exposes earlier CPU flags allowing the use of the vector cryptography
extensions.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c1956dc29b..48d584ab0d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1714,6 +1714,16 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
+ /* Vector cryptography extensions */
+ DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
+ DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
+ DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
+ DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
+ DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
+ DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
+ DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
+ DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.31.1
- Re: [PATCH v4 10/17] target/riscv: Add Zvkned ISA extension support, (continued)
- [PATCH v4 11/17] target/riscv: Add Zvknh ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 12/17] target/riscv: Add Zvksh ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 13/17] target/riscv: Add Zvkg ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 14/17] crypto: Create sm4_subword, Max Chou, 2023/06/22
- [PATCH v4 15/17] crypto: Add SM4 constant parameter CK, Max Chou, 2023/06/22
- [PATCH v4 16/17] target/riscv: Add Zvksed ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 17/17] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties,
Max Chou <=