Re: [PATCH] sungem: Add WOL MMIO

[Cédric Le Goater]

On 6/25/23 22:16, Nicholas Piggin wrote:
> Apple sungem devices are expected to have WOL MMIO registers.
> Add a region to prevent transaction failures, and implement the
> WOL-disable CSR write because the Linux driver reset writes
> this.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.

> ---
> This fixes the failed MMIO error in the Linux sungem driver reset
> when it clears the WOL CSR.
>
> Thanks,
> Nick
>
>   hw/net/sungem.c     | 52 +++++++++++++++++++++++++++++++++++++++++++++
>   hw/net/trace-events |  2 ++
>   2 files changed, 54 insertions(+)
>
> diff --git a/hw/net/sungem.c b/hw/net/sungem.c
> index eb01520790..e0e8e5ae41 100644
> --- a/hw/net/sungem.c
> +++ b/hw/net/sungem.c
> @@ -107,6 +107,15 @@ OBJECT_DECLARE_SIMPLE_TYPE(SunGEMState, SUNGEM)
>   #define RXDMA_FTAG        0x0110UL    /* RX FIFO Tag */
>   #define RXDMA_FSZ         0x0120UL    /* RX FIFO Size */
>   
> +/* WOL Registers */
> +#define SUNGEM_MMIO_WOL_SIZE   0x14
> +
> +#define WOL_MATCH0        0x0000UL
> +#define WOL_MATCH1        0x0004UL
> +#define WOL_MATCH2        0x0008UL
> +#define WOL_MCOUNT        0x000CUL
> +#define WOL_WAKECSR       0x0010UL
> +
>   /* MAC Registers */
>   #define SUNGEM_MMIO_MAC_SIZE   0x200
>   
> @@ -168,6 +177,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(SunGEMState, SUNGEM)
>   #define SUNGEM_MMIO_PCS_SIZE   0x60
>   #define PCS_MIISTAT       0x0004UL    /* PCS MII Status Register */
>   #define PCS_ISTAT         0x0018UL    /* PCS Interrupt Status Reg */
> +
>   #define PCS_SSTATE        0x005CUL    /* Serialink State Register */
>   
>   /* Descriptors */
> @@ -200,6 +210,7 @@ struct SunGEMState {
>       MemoryRegion greg;
>       MemoryRegion txdma;
>       MemoryRegion rxdma;
> +    MemoryRegion wol;
>       MemoryRegion mac;
>       MemoryRegion mif;
>       MemoryRegion pcs;
> @@ -1076,6 +1087,43 @@ static const MemoryRegionOps sungem_mmio_rxdma_ops = {
>       },
>   };
>   
> +static void sungem_mmio_wol_write(void *opaque, hwaddr addr, uint64_t val,
> +                                    unsigned size)
> +{
> +    trace_sungem_mmio_wol_write(addr, val);
> +
> +    switch (addr) {
> +    case WOL_WAKECSR:
> +        if (val != 0) {
> +            qemu_log_mask(LOG_UNIMP, "sungem: WOL not supported\n");
> +        }
> +        break;
> +    default:
> +        qemu_log_mask(LOG_UNIMP, "sungem: WOL not supported\n");
> +    }
> +}
> +
> +static uint64_t sungem_mmio_wol_read(void *opaque, hwaddr addr, unsigned size)
> +{
> +    uint32_t val = -1;
> +
> +    qemu_log_mask(LOG_UNIMP, "sungem: WOL not supported\n");
> +
> +    trace_sungem_mmio_wol_read(addr, val);
> +
> +    return val;
> +}
> +
> +static const MemoryRegionOps sungem_mmio_wol_ops = {
> +    .read = sungem_mmio_wol_read,
> +    .write = sungem_mmio_wol_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .impl = {
> +        .min_access_size = 4,
> +        .max_access_size = 4,
> +    },
> +};
> +
>   static void sungem_mmio_mac_write(void *opaque, hwaddr addr, uint64_t val,
>                                     unsigned size)
>   {
> @@ -1344,6 +1392,10 @@ static void sungem_realize(PCIDevice *pci_dev, Error 
> **errp)
>                             "sungem.rxdma", SUNGEM_MMIO_RXDMA_SIZE);
>       memory_region_add_subregion(&s->sungem, 0x4000, &s->rxdma);
>   
> +    memory_region_init_io(&s->wol, OBJECT(s), &sungem_mmio_wol_ops, s,
> +                          "sungem.wol", SUNGEM_MMIO_WOL_SIZE);
> +    memory_region_add_subregion(&s->sungem, 0x3000, &s->wol);
> +
>       memory_region_init_io(&s->mac, OBJECT(s), &sungem_mmio_mac_ops, s,
>                             "sungem.mac", SUNGEM_MMIO_MAC_SIZE);
>       memory_region_add_subregion(&s->sungem, 0x6000, &s->mac);
> diff --git a/hw/net/trace-events b/hw/net/trace-events
> index e4a98b2c7d..930e5b4293 100644
> --- a/hw/net/trace-events
> +++ b/hw/net/trace-events
> @@ -350,6 +350,8 @@ sungem_mmio_txdma_write(uint64_t addr, uint64_t val) "MMIO txdma 
> write to 0x%"PR
>   sungem_mmio_txdma_read(uint64_t addr, uint64_t val) "MMIO txdma read from 
> 0x%"PRIx64" val=0x%"PRIx64
>   sungem_mmio_rxdma_write(uint64_t addr, uint64_t val) "MMIO rxdma write to 
> 0x%"PRIx64" val=0x%"PRIx64
>   sungem_mmio_rxdma_read(uint64_t addr, uint64_t val) "MMIO rxdma read from 
> 0x%"PRIx64" val=0x%"PRIx64
> +sungem_mmio_wol_write(uint64_t addr, uint64_t val) "MMIO wol write to 0x%"PRIx64" 
> val=0x%"PRIx64
> +sungem_mmio_wol_read(uint64_t addr, uint64_t val) "MMIO wol read from 0x%"PRIx64" 
> val=0x%"PRIx64
>   sungem_mmio_mac_write(uint64_t addr, uint64_t val) "MMIO mac write to 0x%"PRIx64" 
> val=0x%"PRIx64
>   sungem_mmio_mac_read(uint64_t addr, uint64_t val) "MMIO mac read from 0x%"PRIx64" 
> val=0x%"PRIx64
>   sungem_mmio_mif_write(uint64_t addr, uint64_t val) "MMIO mif write to 0x%"PRIx64" 
> val=0x%"PRIx64