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Re: [PATCH 7/7] target/i386: Add new CPU model GraniteRapids
From: |
Igor Mammedov |
Subject: |
Re: [PATCH 7/7] target/i386: Add new CPU model GraniteRapids |
Date: |
Tue, 27 Jun 2023 13:55:23 +0200 |
On Fri, 16 Jun 2023 11:23:11 +0800
Tao Su <tao1.su@linux.intel.com> wrote:
> The GraniteRapids CPU model mainly adds the following new features based
> on SapphireRapids:
>
> - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> - MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
> - SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
> - FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
> - PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
> - PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
Can you point me to a some doc where above features
are are documented as being introduced by GraniteRapids?
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> Tested-by: Xuelian Guo <xuelian.guo@intel.com>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> target/i386/cpu.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 136 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 7faf6dfaee..860106fc24 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3993,6 +3993,142 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> { /* end of list */ },
> },
> },
> + {
> + .name = "GraniteRapids",
> + .level = 0x20,
> + .vendor = CPUID_VENDOR_INTEL,
> + .family = 6,
> + .model = 173,
> + .stepping = 0,
> + /*
> + * please keep the ascending order so that we can have a clear view
> of
> + * bit position of each feature.
> + */
> + .features[FEAT_1_EDX] =
> + CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
> + CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
> + CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
> + CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR
> |
> + CPUID_SSE | CPUID_SSE2,
> + .features[FEAT_1_ECX] =
> + CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
> + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |
> CPUID_EXT_SSE41 |
> + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
> + CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
> + CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C |
> CPUID_EXT_RDRAND,
> + .features[FEAT_8000_0001_EDX] =
> + CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
> + CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
> + .features[FEAT_8000_0001_ECX] =
> + CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
> + .features[FEAT_8000_0008_EBX] =
> + CPUID_8000_0008_EBX_WBNOINVD,
> + .features[FEAT_7_0_EBX] =
> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
> + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> + CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
> + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
> + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
> + CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
> + CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD |
> CPUID_7_0_EBX_SHA_NI |
> + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
> + .features[FEAT_7_0_ECX] =
> + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP |
> CPUID_7_0_ECX_PKU |
> + CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
> + CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
> + CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
> + CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
> + CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
> + .features[FEAT_7_0_EDX] =
> + CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
> + CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
> + CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
> + CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
> + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
> + .features[FEAT_ARCH_CAPABILITIES] =
> + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
> + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
> + MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
> + MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
> + MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
> + .features[FEAT_XSAVE] =
> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
> + .features[FEAT_6_EAX] =
> + CPUID_6_EAX_ARAT,
> + .features[FEAT_7_1_EAX] =
> + CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
> + CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
> + CPUID_7_1_EAX_AMX_FP16,
> + .features[FEAT_7_1_EDX] =
> + CPUID_7_1_EDX_PREFETCHITI,
> + .features[FEAT_7_2_EDX] =
> + CPUID_7_2_EDX_MCDT_NO,
> + .features[FEAT_VMX_BASIC] =
> + MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
> + .features[FEAT_VMX_ENTRY_CTLS] =
> + VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
> + VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
> + VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
> + .features[FEAT_VMX_EPT_VPID_CAPS] =
> + MSR_VMX_EPT_EXECONLY |
> + MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
> + MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
> + MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
> + MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT |
> MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
> + MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
> + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
> + MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
> + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
> + .features[FEAT_VMX_EXIT_CTLS] =
> + VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
> + VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> + VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> + VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> + VMX_VM_EXIT_LOAD_IA32_EFER |
> VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> + .features[FEAT_VMX_MISC] =
> + MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> + MSR_VMX_MISC_VMWRITE_VMEXIT,
> + .features[FEAT_VMX_PINBASED_CTLS] =
> + VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
> + VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
> + VMX_PIN_BASED_POSTED_INTR,
> + .features[FEAT_VMX_PROCBASED_CTLS] =
> + VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
> + VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
> + VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
> + VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
> + VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING
> |
> + VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING
> |
> + VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
> + VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
> + VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
> + VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
> + VMX_CPU_BASED_PAUSE_EXITING |
> + VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
> + .features[FEAT_VMX_SECONDARY_CTLS] =
> + VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
> + VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
> + VMX_SECONDARY_EXEC_RDTSCP |
> + VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
> + VMX_SECONDARY_EXEC_ENABLE_VPID |
> VMX_SECONDARY_EXEC_WBINVD_EXITING |
> + VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
> + VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
> + VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
> + VMX_SECONDARY_EXEC_RDRAND_EXITING |
> + VMX_SECONDARY_EXEC_ENABLE_INVPCID |
> + VMX_SECONDARY_EXEC_ENABLE_VMFUNC |
> VMX_SECONDARY_EXEC_SHADOW_VMCS |
> + VMX_SECONDARY_EXEC_RDSEED_EXITING |
> VMX_SECONDARY_EXEC_ENABLE_PML |
> + VMX_SECONDARY_EXEC_XSAVES,
> + .features[FEAT_VMX_VMFUNC] =
> + MSR_VMX_VMFUNC_EPT_SWITCHING,
> + .xlevel = 0x80000008,
> + .model_id = "Intel Xeon Processor (GraniteRapids)",
> + .versions = (X86CPUVersionDefinition[]) {
> + { .version = 1 },
> + { /* end of list */ },
> + },
> + },
> {
> .name = "Denverton",
> .level = 21,
- Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model, (continued)
[PATCH 6/7] target/i386: Add new CPU model EmeraldRapids, Tao Su, 2023/06/15
[PATCH 7/7] target/i386: Add new CPU model GraniteRapids, Tao Su, 2023/06/15
- Re: [PATCH 7/7] target/i386: Add new CPU model GraniteRapids,
Igor Mammedov <=
Re: [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids, Wang, Lei, 2023/06/16