Re: [PATCH 00/16] target/riscv: Allow building without TCG (KVM-only so far)

[Daniel Henrique Barboza]

Phil,

Can you rebase this on top of Alistair's riscv-to-apply.next?

https://github.com/alistair23/qemu/tree/riscv-to-apply.next

There's a trivial conflict in patch 8 and a not so trivial conflict in patch 14
that I'd rather let you deal with it.

Also, can you take a look at these KVM patches to see if there's a potential
design conflict with what you're doing here?

"[PATCH v5 00/19] target/riscv, KVM: fixes and enhancements"

We're missing a few details in one of the patches and it seems good to go. I am
doing some stuff there that I'm unsure if it will compromise the work you're
doing here (e.g. creating kvm user properties by using TCG user properties). In
a quick glance at your series I think we'll be fine, but better safe than sorry.

I guess I'll wait for you to send a rebased version of this series and apply
mine on top of it to see what happens. That would be a good test.


Thanks,


Daniel


On 6/26/23 20:19, Philippe Mathieu-Daudé wrote:
> Hi,
>
> this series reorder TCG specific code in order to easily
> build a KVM-only binary. sysemu specific code is also
> moved around, to help noticing invalid uses from user
> emulation. Last patch adds a new job to our CI to avoid
> this to bitrot.
>
> Please review,
>
> Phil.
>
> Philippe Mathieu-Daudé (16):
>    target/riscv: Remove unused 'instmap.h' header in translate.c
>    target/riscv: Restrict KVM-specific fields from ArchCPU
>    target/riscv: Restrict sysemu specific header to user emulation
>    target/riscv: Restrict 'rv128' machine to TCG accelerator
>    target/riscv: Move sysemu-specific files to target/riscv/sysemu/
>    target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu
>    target/riscv: Move TCG-specific files to target/riscv/tcg/
>    target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c
>    target/riscv: Expose some 'trigger' prototypes from debug.c
>    target/riscv: Extract TCG-specific code from debug.c
>    target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/
>    target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c
>    target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c
>    target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c
>    target/riscv: Restrict TCG-specific prototype declarations
>    gitlab-ci.d/crossbuilds: Add KVM riscv64 cross-build jobs
>
>   target/riscv/cpu.h                            |   29 +-
>   target/riscv/internals.h                      |    4 +
>   target/riscv/{ => sysemu}/debug.h             |    6 +
>   target/riscv/{ => sysemu}/instmap.h           |    0
>   target/riscv/{ => sysemu}/kvm_riscv.h         |    0
>   target/riscv/{ => sysemu}/pmp.h               |    0
>   target/riscv/{ => sysemu}/pmu.h               |    0
>   target/riscv/{ => sysemu}/time_helper.h       |    0
>   target/riscv/{ => tcg}/XVentanaCondOps.decode |    0
>   target/riscv/{ => tcg}/insn16.decode          |    0
>   target/riscv/{ => tcg}/insn32.decode          |    0
>   target/riscv/{ => tcg}/xthead.decode          |    0
>   hw/riscv/virt.c                               |    2 +-
>   target/riscv/cpu.c                            |   35 +-
>   target/riscv/cpu_helper.c                     | 1692 +----------------
>   target/riscv/csr.c                            |    6 +-
>   target/riscv/{ => sysemu}/arch_dump.c         |    0
>   target/riscv/sysemu/cpu_helper.c              |  863 +++++++++
>   target/riscv/{ => sysemu}/debug.c             |  153 +-
>   target/riscv/{ => sysemu}/kvm-stub.c          |    0
>   target/riscv/{ => sysemu}/kvm.c               |    0
>   target/riscv/{ => sysemu}/machine.c           |    8 +-
>   target/riscv/{ => sysemu}/monitor.c           |    0
>   target/riscv/{ => sysemu}/pmp.c               |    0
>   target/riscv/{ => sysemu}/pmu.c               |    0
>   target/riscv/{ => sysemu}/riscv-qmp-cmds.c    |    0
>   target/riscv/{ => sysemu}/time_helper.c       |    0
>   target/riscv/{ => tcg}/bitmanip_helper.c      |    0
>   target/riscv/tcg/cpu.c                        |   97 +
>   target/riscv/{ => tcg}/crypto_helper.c        |    0
>   target/riscv/{ => tcg}/fpu_helper.c           |    0
>   target/riscv/{ => tcg}/m128_helper.c          |    0
>   target/riscv/{ => tcg}/op_helper.c            |    0
>   target/riscv/tcg/sysemu/cpu_helper.c          |  766 ++++++++
>   target/riscv/tcg/sysemu/debug.c               |  165 ++
>   target/riscv/tcg/tcg-stub.c                   |   31 +
>   target/riscv/{ => tcg}/translate.c            |    1 -
>   target/riscv/{ => tcg}/vector_helper.c        |    0
>   target/riscv/{ => tcg}/zce_helper.c           |    0
>   .gitlab-ci.d/crossbuilds.yml                  |    8 +
>   target/riscv/meson.build                      |   33 +-
>   target/riscv/sysemu/meson.build               |   14 +
>   target/riscv/tcg/meson.build                  |   22 +
>   target/riscv/tcg/sysemu/meson.build           |    4 +
>   44 files changed, 2046 insertions(+), 1893 deletions(-)
>   rename target/riscv/{ => sysemu}/debug.h (96%)
>   rename target/riscv/{ => sysemu}/instmap.h (100%)
>   rename target/riscv/{ => sysemu}/kvm_riscv.h (100%)
>   rename target/riscv/{ => sysemu}/pmp.h (100%)
>   rename target/riscv/{ => sysemu}/pmu.h (100%)
>   rename target/riscv/{ => sysemu}/time_helper.h (100%)
>   rename target/riscv/{ => tcg}/XVentanaCondOps.decode (100%)
>   rename target/riscv/{ => tcg}/insn16.decode (100%)
>   rename target/riscv/{ => tcg}/insn32.decode (100%)
>   rename target/riscv/{ => tcg}/xthead.decode (100%)
>   rename target/riscv/{ => sysemu}/arch_dump.c (100%)
>   create mode 100644 target/riscv/sysemu/cpu_helper.c
>   rename target/riscv/{ => sysemu}/debug.c (83%)
>   rename target/riscv/{ => sysemu}/kvm-stub.c (100%)
>   rename target/riscv/{ => sysemu}/kvm.c (100%)
>   rename target/riscv/{ => sysemu}/machine.c (98%)
>   rename target/riscv/{ => sysemu}/monitor.c (100%)
>   rename target/riscv/{ => sysemu}/pmp.c (100%)
>   rename target/riscv/{ => sysemu}/pmu.c (100%)
>   rename target/riscv/{ => sysemu}/riscv-qmp-cmds.c (100%)
>   rename target/riscv/{ => sysemu}/time_helper.c (100%)
>   rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
>   create mode 100644 target/riscv/tcg/cpu.c
>   rename target/riscv/{ => tcg}/crypto_helper.c (100%)
>   rename target/riscv/{ => tcg}/fpu_helper.c (100%)
>   rename target/riscv/{ => tcg}/m128_helper.c (100%)
>   rename target/riscv/{ => tcg}/op_helper.c (100%)
>   create mode 100644 target/riscv/tcg/sysemu/cpu_helper.c
>   create mode 100644 target/riscv/tcg/sysemu/debug.c
>   create mode 100644 target/riscv/tcg/tcg-stub.c
>   rename target/riscv/{ => tcg}/translate.c (99%)
>   rename target/riscv/{ => tcg}/vector_helper.c (100%)
>   rename target/riscv/{ => tcg}/zce_helper.c (100%)
>   create mode 100644 target/riscv/sysemu/meson.build
>   create mode 100644 target/riscv/tcg/meson.build
>   create mode 100644 target/riscv/tcg/sysemu/meson.build