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[PATCH v2 4/4] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 4/4] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu |
Date: |
Wed, 28 Jun 2023 08:32:34 +0200 |
riscv_cpu_do_interrupt() is not reachable on user emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.h | 5 +++--
target/riscv/cpu_helper.c | 7 ++-----
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cc20ee25a7..ab6aa7e3ea 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -409,7 +409,6 @@ extern const char * const riscv_int_regnamesh[];
extern const char * const riscv_fpr_regnames[];
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
-void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
@@ -442,6 +441,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error
**errp);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+void riscv_cpu_do_interrupt(CPUState *cpu);
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -465,7 +465,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env,
uint32_t priv,
void *rmw_fn_arg);
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
-#endif
+#endif /* !CONFIG_USER_ONLY */
+
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3c28396eaf..3f5ba2b4ef 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1580,7 +1580,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState
*env,
return xinsn;
}
-#endif /* !CONFIG_USER_ONLY */
/*
* Handle Traps
@@ -1590,8 +1589,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState
*env,
*/
void riscv_cpu_do_interrupt(CPUState *cs)
{
-#if !defined(CONFIG_USER_ONLY)
-
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
bool write_gva = false;
@@ -1784,6 +1781,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->two_stage_lookup = false;
env->two_stage_indirect_lookup = false;
-#endif
- cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
}
+
+#endif /* !CONFIG_USER_ONLY */
--
2.38.1