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Re: [PATCH qemu] aspeed add montblanc bmc reference from fuji


From: Sittisak Sinprem
Subject: Re: [PATCH qemu] aspeed add montblanc bmc reference from fuji
Date: Thu, 29 Jun 2023 09:57:17 +0700

Hi Cédric,

I had fixed the function name to support in current branch,
but facing about below error while starting

./build/qemu-system-arm -machine montblanc-bmc  -drive file=~/flash-montblanc,format=raw,if=mtd -nographic -netdev tap,id=netdev0,script=no,downscript=no,ifname=tap0 -net nic,netdev=netdev0,model=ftgmac100
 
qemu-system-arm: device requires 134217728 bytes, block backend provides 27726336 bytes



On Wed, Jun 28, 2023 at 11:34 PM Cédric Le Goater <clg@kaod.org> wrote:
On 6/28/23 12:07, Sittisak Sinprem wrote:
> Got it Cedric, I just know for it,
>
> I am fixing, and will re-send the patch as V2.

Could you please use the patch below and send in your series ?

Thanks,

C.


 From cfbc865ffe8a4dffe4ac764eb10416aa906a7170 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
Date: Wed, 28 Jun 2023 18:32:20 +0200
Subject: [PATCH] aspeed: Introduce ASPEED_RAM_SIZE helper for 32-bit hosts
  limitation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On 32-bit hosts, RAM has a 2047 MB limit. Use a macro to define the
default ram size of machines (AST2600 SoC) that can have 2 GB.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
  hw/arm/aspeed.c | 21 +++++++++------------
  1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index eefd2e275015..0ae252232597 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -49,6 +49,13 @@ struct AspeedMachineState {
      uint32_t hw_strap1;
  };

+/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
+#if HOST_LONG_BITS == 32
+#define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
+#else
+#define ASPEED_RAM_SIZE(sz) (sz)
+#endif
+
  /* Palmetto hardware value: 0x120CE416 */
  #define PALMETTO_BMC_HW_STRAP1 (                                        \
          SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
@@ -1504,12 +1511,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
      aspeed_machine_ast2600_class_init(oc, data);
  };

-/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
-#if HOST_LONG_BITS == 32
-#define FUJI_BMC_RAM_SIZE (1 * GiB)
-#else
-#define FUJI_BMC_RAM_SIZE (2 * GiB)
-#endif
+#define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)

  static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
  {
@@ -1533,12 +1535,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
      aspeed_machine_ast2600_class_init(oc, data);
  };

-/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
-#if HOST_LONG_BITS == 32
-#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
-#else
-#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
-#endif
+#define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)

  static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
  {
--
2.41.0



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