Re: [PATCH v6 10/15] target/riscv: Add Zvknh ISA extension support

[Max Chou]

On 2023/6/28 5:14 PM, Richard Henderson wrote:

> On 6/27/23 19:45, Max Chou wrote:
> > +void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2, 
> > CPURISCVState *env,
> > +                        uint32_t desc)
> > +{
> > +    uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
> > +    uint32_t esz = sew == MO_64 ? 8 : 4;
> > +    uint32_t total_elems;
> > +    uint32_t vta = vext_vta(desc);
> > +
> > +    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
> > +        if (sew == MO_64) {
> > +            vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 
> > 4 * i,
> > +                      (((uint64_t *)vs1) + 4 * i));
> > +        } else {
> > +            vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 
> > 4 * i,
> > +                      (((uint32_t *)vs1) + 4 * i));
> > +        }
> > +    }
>
> You should have two separate functions for two separate VSEW, so that 
> you do not need to pass the value nor decode the value here. The 
> selection of SEW should happen during translation using DisasContext.sew.
>
>
> r~
Thanks for the suggestion. I'll provide the v7 patch set for this.

Thanks,
Max