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[PATCH v2 05/46] target/loongarch: Implement xvreplgr2vr
From: |
Song Gao |
Subject: |
[PATCH v2 05/46] target/loongarch: Implement xvreplgr2vr |
Date: |
Fri, 30 Jun 2023 15:58:23 +0800 |
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 10 ++++++++++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +++++
target/loongarch/insn_trans/trans_lsx.c.inc | 13 +++++++------
target/loongarch/insns.decode | 5 +++++
4 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index d8b62ba532..c47f455ed0 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1708,6 +1708,11 @@ static void output_vvv_x(DisasContext *ctx, arg_vvv * a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d, x%d", a->vd, a->vj, a->vk);
}
+static void output_vr_x(DisasContext *ctx, arg_vr *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "x%d, r%d", a->vd, a->rj);
+}
+
INSN_LASX(xvadd_b, vvv)
INSN_LASX(xvadd_h, vvv)
INSN_LASX(xvadd_w, vvv)
@@ -1718,3 +1723,8 @@ INSN_LASX(xvsub_h, vvv)
INSN_LASX(xvsub_w, vvv)
INSN_LASX(xvsub_d, vvv)
INSN_LASX(xvsub_q, vvv)
+
+INSN_LASX(xvreplgr2vr_b, vr)
+INSN_LASX(xvreplgr2vr_h, vr)
+INSN_LASX(xvreplgr2vr_w, vr)
+INSN_LASX(xvreplgr2vr_d, vr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 86ba296a73..9bbf6c48ec 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -46,3 +46,8 @@ TRANS(xvsub_b, gvec_vvv, 32, MO_8, tcg_gen_gvec_sub)
TRANS(xvsub_h, gvec_vvv, 32, MO_16, tcg_gen_gvec_sub)
TRANS(xvsub_w, gvec_vvv, 32, MO_32, tcg_gen_gvec_sub)
TRANS(xvsub_d, gvec_vvv, 32, MO_64, tcg_gen_gvec_sub)
+
+TRANS(xvreplgr2vr_b, gvec_dup, 32, MO_8)
+TRANS(xvreplgr2vr_h, gvec_dup, 32, MO_16)
+TRANS(xvreplgr2vr_w, gvec_dup, 32, MO_32)
+TRANS(xvreplgr2vr_d, gvec_dup, 32, MO_64)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 63061bd4a1..4667dba4b4 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -4058,20 +4058,21 @@ static bool trans_vpickve2gr_du(DisasContext *ctx,
arg_rv_i *a)
return true;
}
-static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
+static bool gvec_dup(DisasContext *ctx, arg_vr *a, uint32_t oprsz, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+
CHECK_VEC;
tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
- 16, ctx->vl/8, src);
+ oprsz, ctx->vl / 8, src);
return true;
}
-TRANS(vreplgr2vr_b, gvec_dup, MO_8)
-TRANS(vreplgr2vr_h, gvec_dup, MO_16)
-TRANS(vreplgr2vr_w, gvec_dup, MO_32)
-TRANS(vreplgr2vr_d, gvec_dup, MO_64)
+TRANS(vreplgr2vr_b, gvec_dup, 16, MO_8)
+TRANS(vreplgr2vr_h, gvec_dup, 16, MO_16)
+TRANS(vreplgr2vr_w, gvec_dup, 16, MO_32)
+TRANS(vreplgr2vr_d, gvec_dup, 16, MO_64)
static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)
{
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index bcc18fb6c5..04bd238995 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1310,3 +1310,8 @@ xvsub_h 0111 01000000 11001 ..... ..... .....
@vvv
xvsub_w 0111 01000000 11010 ..... ..... ..... @vvv
xvsub_d 0111 01000000 11011 ..... ..... ..... @vvv
xvsub_q 0111 01010010 11011 ..... ..... ..... @vvv
+
+xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
+xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
+xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
+xvreplgr2vr_d 0111 01101001 11110 00011 ..... ..... @vr
--
2.39.1
- [PATCH v2 00/46] Add LoongArch LASX instructions, Song Gao, 2023/06/30
- [PATCH v2 02/46] target/loongarch: meson.build support build LASX, Song Gao, 2023/06/30
- [PATCH v2 01/46] target/loongarch: Add LASX data support, Song Gao, 2023/06/30
- [PATCH v2 05/46] target/loongarch: Implement xvreplgr2vr,
Song Gao <=
- [PATCH v2 07/46] target/loongarch: Implement xvneg, Song Gao, 2023/06/30
- [PATCH v2 03/46] target/loongarch: Add CHECK_ASXE maccro for check LASX enable, Song Gao, 2023/06/30
- [PATCH v2 04/46] target/loongarch: Implement xvadd/xvsub, Song Gao, 2023/06/30
- [PATCH v2 09/46] target/loongarch: Implement xvhaddw/xvhsubw, Song Gao, 2023/06/30
- [PATCH v2 06/46] target/loongarch: Implement xvaddi/xvsubi, Song Gao, 2023/06/30
- [PATCH v2 08/46] target/loongarch: Implement xvsadd/xvssub, Song Gao, 2023/06/30
- [PATCH v2 10/46] target/loongarch: Implement xvaddw/xvsubw, Song Gao, 2023/06/30
- [PATCH v2 15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}, Song Gao, 2023/06/30
- [PATCH v2 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}, Song Gao, 2023/06/30
- [PATCH v2 14/46] target/loongarch: Implement xvmax/xvmin, Song Gao, 2023/06/30