From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since QEMU does not support the RISC-V quad-precision floating-point
ISA extension (Q), this patch does not include the instructions that
depend on this extension. All other instructions are included in this
patch.
The Zfa specification can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
The Zfa specifciation is frozen and is in public review since May 3, 2023:
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg
The patch also includes a TCG test for the fcvtmod.w.d instruction.
The test cases test for correct results and flag behaviour.
Note, that the Zfa specification requires fcvtmod's flag behaviour
to be identical to a fcvt with the same operands (which is also
tested).
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
This patch depends on float64_to_int64_modulo(), which is provided
by a patchset from Richard Henderson:
https://lists.nongnu.org/archive/html/qemu-devel/2023-05/msg07022.html
Changes in v6:
* Address issues in trans_fmvp_d_x() and trans_fmvh_x_d()
Changes in v5:
* Merge all three commits
* Address issues reported by Richard
Changes in v4:
* Rebase and resolve conflicts
* Fix whitespace issue (thanks Rob)
* Add patch to implemnt fcvtmod.w.d using float64_to_int64_modulo()
* Add (demo) test for fcvtmod.w.d
Changes in v3:
* Add disassembler support
* Enable Zfa by default
* Remove forgotten comments in the decoder
* Fix fli translation code (use movi instead of ld)
* Tested against SPEC CPU2017 fprate
* Use floatN_[min|max] for f[min|max]m.* instructions
Changes in v2:
* Remove calls to mark_fs_dirty() in comparison trans functions
* Rewrite fround(nx) using float*_round_to_int()
* Move fli* to translation unit and fix NaN-boxing of NaN values
* Reimplement FCVTMOD.W.D
* Add use of second register in trans_fmvp_d_x()
disas/riscv.c | 151 +++++++
target/riscv/cpu.c | 8 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/fpu_helper.c | 154 +++++++
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 26 ++
target/riscv/insn_trans/trans_rvzfa.c.inc | 521 ++++++++++++++++++++++
target/riscv/translate.c | 1 +
tests/tcg/riscv64/Makefile.target | 6 +
tests/tcg/riscv64/test-fcvtmod.c | 345 ++++++++++++++
10 files changed, 1232 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzfa.c.inc
create mode 100644 tests/tcg/riscv64/test-fcvtmod.c