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[PULL 16/31] target/loongarch: Extract set_pc() helper
From: |
Song Gao |
Subject: |
[PULL 16/31] target/loongarch: Extract set_pc() helper |
Date: |
Thu, 24 Aug 2023 17:23:54 +0800 |
From: Jiajie Chen <c@jia.je>
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230822071405.35386-9-philmd@linaro.org>
---
target/loongarch/cpu.c | 16 ++++++++--------
target/loongarch/cpu.h | 5 +++++
target/loongarch/gdbstub.c | 2 +-
target/loongarch/op_helper.c | 4 ++--
4 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 822f2a72e5..67eb6c3135 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -81,7 +81,7 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
- env->pc = value;
+ set_pc(env, value);
}
static vaddr loongarch_cpu_get_pc(CPUState *cs)
@@ -168,7 +168,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
set_DERA:
env->CSR_DERA = env->pc;
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
- env->pc = env->CSR_EENTRY + 0x480;
+ set_pc(env, env->CSR_EENTRY + 0x480);
break;
case EXCCODE_INT:
if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
@@ -249,7 +249,8 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
/* Find the highest-priority interrupt. */
vector = 31 - clz32(pending);
- env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
+ set_pc(env, env->CSR_EENTRY + \
+ (EXCCODE_EXTERNAL_INT + vector) * vec_size);
qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
" cause %d\n" " A " TARGET_FMT_lx " D "
@@ -260,10 +261,9 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
env->CSR_ECFG, env->CSR_ESTAT);
} else {
if (tlbfill) {
- env->pc = env->CSR_TLBRENTRY;
+ set_pc(env, env->CSR_TLBRENTRY);
} else {
- env->pc = env->CSR_EENTRY;
- env->pc += EXCODE_MCODE(cause) * vec_size;
+ set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size);
}
qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
@@ -324,7 +324,7 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
CPULoongArchState *env = &cpu->env;
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
- env->pc = tb->pc;
+ set_pc(env, tb->pc);
}
static void loongarch_restore_state_to_opc(CPUState *cs,
@@ -334,7 +334,7 @@ static void loongarch_restore_state_to_opc(CPUState *cs,
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
- env->pc = data[0];
+ set_pc(env, data[0]);
}
#endif /* CONFIG_TCG */
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 72109095e4..e1562695e8 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -443,6 +443,11 @@ static inline bool is_va32(CPULoongArchState *env)
return va32;
}
+static inline void set_pc(CPULoongArchState *env, uint64_t value)
+{
+ env->pc = value;
+}
+
/*
* LoongArch CPUs hardware flags.
*/
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index a462e25737..e20b20f99b 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -77,7 +77,7 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
env->gpr[n] = tmp;
length = read_length;
} else if (n == 33) {
- env->pc = tmp;
+ set_pc(env, tmp);
length = read_length;
}
return length;
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index 60335a05e2..cf84f20aba 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -114,14 +114,14 @@ void helper_ertn(CPULoongArchState *env)
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,
0);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
- env->pc = env->CSR_TLBRERA;
+ set_pc(env, env->CSR_TLBRERA);
qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n",
__func__, env->CSR_TLBRERA);
} else {
csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
- env->pc = env->CSR_ERA;
+ set_pc(env, env->CSR_ERA);
qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n",
__func__, env->CSR_ERA);
}
--
2.39.1
- [PULL 04/31] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU, (continued)
- [PULL 04/31] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU, Song Gao, 2023/08/24
- [PULL 08/31] target/loongarch: Add GDB support for loongarch32 mode, Song Gao, 2023/08/24
- [PULL 06/31] target/loongarch: Add function to check current arch, Song Gao, 2023/08/24
- [PULL 01/31] target/loongarch: Log I/O write accesses to CSR registers, Song Gao, 2023/08/24
- [PULL 22/31] hw/loongarch: Remove restriction of la464 cores in the virt machine, Song Gao, 2023/08/24
- [PULL 23/31] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions, Song Gao, 2023/08/24
- [PULL 15/31] target/loongarch: Extract make_address_pc() helper, Song Gao, 2023/08/24
- [PULL 18/31] target/loongarch: Sign extend results in VA32 mode, Song Gao, 2023/08/24
- [PULL 27/31] target/loongarch: Add avail_IOCSR to check iocsr instructions, Song Gao, 2023/08/24
- [PULL 12/31] target/loongarch: Add LA64 & VA32 to DisasContext, Song Gao, 2023/08/24
- [PULL 16/31] target/loongarch: Extract set_pc() helper,
Song Gao <=
- [PULL 20/31] target/loongarch: Add avail_64 to check la64-only instructions, Song Gao, 2023/08/24
- [PULL 24/31] target/loongarch: Add avail_LSPW to check LSPW instructions, Song Gao, 2023/08/24
- [PULL 29/31] hw/intc/loongarch_pch: fix edge triggered irq handling, Song Gao, 2023/08/24
- [PULL 25/31] target/loongarch: Add avail_LAM to check atomic instructions, Song Gao, 2023/08/24
- [PULL 17/31] target/loongarch: Truncate high 32 bits of address in VA32 mode, Song Gao, 2023/08/24
- [PULL 21/31] target/loongarch: Add LoongArch32 cpu la132, Song Gao, 2023/08/24
- [PULL 19/31] target/loongarch: Add a check parameter to the TRANS macro, Song Gao, 2023/08/24
- [PULL 11/31] target/loongarch: Support LoongArch32 VPPN, Song Gao, 2023/08/24
- [PULL 26/31] target/loongarch: Add avail_LSX to check LSX instructions, Song Gao, 2023/08/24
- [PULL 31/31] hw/loongarch: Fix ACPI processor id off-by-one error, Song Gao, 2023/08/24