qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes


From: Alistair Francis
Subject: Re: [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
Date: Mon, 4 Sep 2023 11:05:33 +1000

On Wed, Aug 30, 2023 at 7:50 AM <leon@is.currently.online> wrote:
>
> From: Leon Schuermann <leons@opentitan.org>
>
> When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
> configuration lock bits must not apply. While this behavior is
> implemented for the pmpcfgX CSRs, this bit is not respected for
> changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
> writes work even on locked regions when the global rule-lock bypass is
> enabled.
>
> Signed-off-by: Leon Schuermann <leons@opentitan.org>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/pmp.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 9d8db493e6..5e60c26031 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
>   */
>  static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
>  {
> +    /* mseccfg.RLB is set */
> +    if (MSECCFG_RLB_ISSET(env)) {
> +        return 0;
> +    }
>
>      if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
>          return 1;
>
> base-commit: a8fc5165aab02f328ccd148aafec1e59fd1426eb
> --
> 2.34.1
>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]