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[PATCH RESEND v5 15/57] target/loongarch: Implement xvreplgr2vr
From: |
Song Gao |
Subject: |
[PATCH RESEND v5 15/57] target/loongarch: Implement xvreplgr2vr |
Date: |
Thu, 7 Sep 2023 16:31:16 +0800 |
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/insns.decode | 5 ++++
target/loongarch/disas.c | 10 +++++++
target/loongarch/insn_trans/trans_vec.c.inc | 29 ++++++++++++++++-----
3 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index bcc18fb6c5..04bd238995 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1310,3 +1310,8 @@ xvsub_h 0111 01000000 11001 ..... ..... .....
@vvv
xvsub_w 0111 01000000 11010 ..... ..... ..... @vvv
xvsub_d 0111 01000000 11011 ..... ..... ..... @vvv
xvsub_q 0111 01010010 11011 ..... ..... ..... @vvv
+
+xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
+xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
+xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
+xvreplgr2vr_d 0111 01101001 11110 00011 ..... ..... @vr
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index d8b62ba532..c47f455ed0 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1708,6 +1708,11 @@ static void output_vvv_x(DisasContext *ctx, arg_vvv * a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d, x%d", a->vd, a->vj, a->vk);
}
+static void output_vr_x(DisasContext *ctx, arg_vr *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "x%d, r%d", a->vd, a->rj);
+}
+
INSN_LASX(xvadd_b, vvv)
INSN_LASX(xvadd_h, vvv)
INSN_LASX(xvadd_w, vvv)
@@ -1718,3 +1723,8 @@ INSN_LASX(xvsub_h, vvv)
INSN_LASX(xvsub_w, vvv)
INSN_LASX(xvsub_d, vvv)
INSN_LASX(xvsub_q, vvv)
+
+INSN_LASX(xvreplgr2vr_b, vr)
+INSN_LASX(xvreplgr2vr_h, vr)
+INSN_LASX(xvreplgr2vr_w, vr)
+INSN_LASX(xvreplgr2vr_d, vr)
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc
b/target/loongarch/insn_trans/trans_vec.c.inc
index 47cf053e0a..a7323e0490 100644
--- a/target/loongarch/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
@@ -4407,27 +4407,42 @@ static bool trans_vpickve2gr_du(DisasContext *ctx,
arg_rv_i *a)
return true;
}
-static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
+static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
+ uint32_t oprsz, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
- if (!avail_LSX(ctx)) {
- return false;
- }
+ tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
+ oprsz, ctx->vl/8, src);
+ return true;
+}
+static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
+{
if (!check_vec(ctx, 16)) {
return true;
}
- tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
- 16, ctx->vl/8, src);
- return true;
+ return gvec_dup_vl(ctx, a, 16, mop);
+}
+
+static bool gvec_dupx(DisasContext *ctx, arg_vr *a, MemOp mop)
+{
+ if (!check_vec(ctx, 32)) {
+ return true;
+ }
+
+ return gvec_dup_vl(ctx, a, 32, mop);
}
TRANS(vreplgr2vr_b, LSX, gvec_dup, MO_8)
TRANS(vreplgr2vr_h, LSX, gvec_dup, MO_16)
TRANS(vreplgr2vr_w, LSX, gvec_dup, MO_32)
TRANS(vreplgr2vr_d, LSX, gvec_dup, MO_64)
+TRANS(xvreplgr2vr_b, LASX, gvec_dupx, MO_8)
+TRANS(xvreplgr2vr_h, LASX, gvec_dupx, MO_16)
+TRANS(xvreplgr2vr_w, LASX, gvec_dupx, MO_32)
+TRANS(xvreplgr2vr_d, LASX, gvec_dupx, MO_64)
static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)
{
--
2.39.1
- Re: [PATCH RESEND v5 16/57] target/loongarch: Implement xvaddi/xvsubi, (continued)
- [PATCH RESEND v5 14/57] target/loongarch: Implement xvadd/xvsub, Song Gao, 2023/09/07
- [PATCH RESEND v5 19/57] target/loongarch: Implement xvhaddw/xvhsubw, Song Gao, 2023/09/07
- [PATCH RESEND v5 21/57] target/loongarch: Implement xavg/xvagr, Song Gao, 2023/09/07
- [PATCH RESEND v5 23/57] target/loongarch: Implement xvadda, Song Gao, 2023/09/07
- [PATCH RESEND v5 15/57] target/loongarch: Implement xvreplgr2vr,
Song Gao <=
- [PATCH RESEND v5 18/57] target/loongarch: Implement xvsadd/xvssub, Song Gao, 2023/09/07
- [PATCH RESEND v5 17/57] target/loongarch: Implement xvneg, Song Gao, 2023/09/07
- [PATCH RESEND v5 25/57] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}, Song Gao, 2023/09/07
- [PATCH RESEND v5 27/57] target/loongarch; Implement xvdiv/xvmod, Song Gao, 2023/09/07
- [PATCH RESEND v5 28/57] target/loongarch: Implement xvsat, Song Gao, 2023/09/07
- [PATCH RESEND v5 29/57] target/loongarch: Implement xvexth, Song Gao, 2023/09/07
- [PATCH RESEND v5 30/57] target/loongarch: Implement vext2xv, Song Gao, 2023/09/07
- [PATCH RESEND v5 32/57] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz, Song Gao, 2023/09/07