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[PATCH RESEND v5 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2
From: |
Song Gao |
Subject: |
[PATCH RESEND v5 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr |
Date: |
Thu, 7 Sep 2023 16:31:52 +0800 |
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/insns.decode | 7 +++
target/loongarch/disas.c | 17 ++++++++
target/loongarch/insn_trans/trans_vec.c.inc | 48 +++++++++++++++++++++
3 files changed, 72 insertions(+)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index ad6751fdfb..bb3bb447ae 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1976,6 +1976,13 @@ xvsetallnez_h 0111 01101001 11001 01101 ..... 00 ...
@cv
xvsetallnez_w 0111 01101001 11001 01110 ..... 00 ... @cv
xvsetallnez_d 0111 01101001 11001 01111 ..... 00 ... @cv
+xvinsgr2vr_w 0111 01101110 10111 10 ... ..... ..... @vr_ui3
+xvinsgr2vr_d 0111 01101110 10111 110 .. ..... ..... @vr_ui2
+xvpickve2gr_w 0111 01101110 11111 10 ... ..... ..... @rv_ui3
+xvpickve2gr_d 0111 01101110 11111 110 .. ..... ..... @rv_ui2
+xvpickve2gr_wu 0111 01101111 00111 10 ... ..... ..... @rv_ui3
+xvpickve2gr_du 0111 01101111 00111 110 .. ..... ..... @rv_ui2
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index abe113b150..04f9f9fa4b 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1738,6 +1738,16 @@ static void output_vv_x(DisasContext *ctx, arg_vv *a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d", a->vd, a->vj);
}
+static void output_vr_i_x(DisasContext *ctx, arg_vr_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "x%d, r%d, 0x%x", a->vd, a->rj, a->imm);
+}
+
+static void output_rv_i_x(DisasContext *ctx, arg_rv_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, x%d, 0x%x", a->rd, a->vj, a->imm);
+}
+
INSN_LASX(xvadd_b, vvv)
INSN_LASX(xvadd_h, vvv)
INSN_LASX(xvadd_w, vvv)
@@ -2497,6 +2507,13 @@ INSN_LASX(xvsetallnez_h, cv)
INSN_LASX(xvsetallnez_w, cv)
INSN_LASX(xvsetallnez_d, cv)
+INSN_LASX(xvinsgr2vr_w, vr_i)
+INSN_LASX(xvinsgr2vr_d, vr_i)
+INSN_LASX(xvpickve2gr_w, rv_i)
+INSN_LASX(xvpickve2gr_d, rv_i)
+INSN_LASX(xvpickve2gr_wu, rv_i)
+INSN_LASX(xvpickve2gr_du, rv_i)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc
b/target/loongarch/insn_trans/trans_vec.c.inc
index b68daa53ae..bf44a4d1fc 100644
--- a/target/loongarch/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
@@ -5268,6 +5268,54 @@ static bool trans_vpickve2gr_du(DisasContext *ctx,
arg_rv_i *a)
return true;
}
+static bool trans_xvinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
+{
+ if (!avail_LASX(ctx)) {
+ return false;
+ }
+ return trans_vinsgr2vr_w(ctx, a);
+}
+
+static bool trans_xvinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
+{
+ if (!avail_LASX(ctx)) {
+ return false;
+ }
+ return trans_vinsgr2vr_d(ctx, a);
+}
+
+static bool trans_xvpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
+{
+ if (!avail_LASX(ctx)) {
+ return false;
+ }
+ return trans_vpickve2gr_w(ctx, a);
+}
+
+static bool trans_xvpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
+{
+ if (!avail_LASX(ctx)) {
+ return false;
+ }
+ return trans_vpickve2gr_d(ctx, a);
+}
+
+static bool trans_xvpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
+{
+ if (!avail_LASX(ctx)) {
+ return false;
+ }
+ return trans_vpickve2gr_wu(ctx, a);
+}
+
+static bool trans_xvpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
+{
+ if (!avail_LASX(ctx)) {
+ return false;
+ }
+ return trans_vpickve2gr_du(ctx, a);
+}
+
static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
uint32_t oprsz, MemOp mop)
{
--
2.39.1
- [PATCH RESEND v5 39/57] target/loongarch: Implement xvsrlrn xvsrarn, (continued)
- [PATCH RESEND v5 39/57] target/loongarch: Implement xvsrlrn xvsrarn, Song Gao, 2023/09/07
- [PATCH RESEND v5 38/57] target/loongarch: Implement xvsrln xvsran, Song Gao, 2023/09/07
- [PATCH RESEND v5 42/57] target/loongarch: Implement xvclo xvclz, Song Gao, 2023/09/07
- [PATCH RESEND v5 46/57] target/loongarch: Implement LASX fpu arith instructions, Song Gao, 2023/09/07
- [PATCH RESEND v5 41/57] target/loongarch: Implement xvssrlrn xvssrarn, Song Gao, 2023/09/07
- [PATCH RESEND v5 40/57] target/loongarch: Implement xvssrln xvssran, Song Gao, 2023/09/07
- [PATCH RESEND v5 47/57] target/loongarch: Implement LASX fpu fcvt instructions, Song Gao, 2023/09/07
- [PATCH RESEND v5 49/57] target/loongarch: Implement xvfcmp, Song Gao, 2023/09/07
- [PATCH RESEND v5 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr,
Song Gao <=
- [PATCH RESEND v5 45/57] target/loongarch: Implement xvfrstp, Song Gao, 2023/09/07
- [PATCH RESEND v5 55/57] target/loongarch: Implement xvld xvst, Song Gao, 2023/09/07
- [PATCH RESEND v5 50/57] target/loongarch: Implement xvbitsel xvset, Song Gao, 2023/09/07
- [PATCH RESEND v5 57/57] target/loongarch: CPUCFG support LASX, Song Gao, 2023/09/07
- [PATCH RESEND v5 53/57] target/loongarch: Implement xvpack xvpick xvilv{l/h}, Song Gao, 2023/09/07
- [PATCH RESEND v5 52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve, Song Gao, 2023/09/07