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[PATCH RESEND v5 31/57] target/loongarch: Implement xvsigncov
From: |
Song Gao |
Subject: |
[PATCH RESEND v5 31/57] target/loongarch: Implement xvsigncov |
Date: |
Thu, 7 Sep 2023 16:31:32 +0800 |
This patch includes:
- XVSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/insns.decode | 5 +++++
target/loongarch/disas.c | 5 +++++
target/loongarch/insn_trans/trans_vec.c.inc | 4 ++++
3 files changed, 14 insertions(+)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index db1a6689f0..7bbda1a142 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1593,6 +1593,11 @@ vext2xv_wu_hu 0111 01101001 11110 01101 ..... .....
@vv
vext2xv_du_hu 0111 01101001 11110 01110 ..... ..... @vv
vext2xv_du_wu 0111 01101001 11110 01111 ..... ..... @vv
+xvsigncov_b 0111 01010010 11100 ..... ..... ..... @vvv
+xvsigncov_h 0111 01010010 11101 ..... ..... ..... @vvv
+xvsigncov_w 0111 01010010 11110 ..... ..... ..... @vvv
+xvsigncov_d 0111 01010010 11111 ..... ..... ..... @vvv
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 714b97e238..1f01ec99d5 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2010,6 +2010,11 @@ INSN_LASX(vext2xv_wu_hu, vv)
INSN_LASX(vext2xv_du_hu, vv)
INSN_LASX(vext2xv_du_wu, vv)
+INSN_LASX(xvsigncov_b, vvv)
+INSN_LASX(xvsigncov_h, vvv)
+INSN_LASX(xvsigncov_w, vvv)
+INSN_LASX(xvsigncov_d, vvv)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc
b/target/loongarch/insn_trans/trans_vec.c.inc
index 57a1c823cf..604e85b654 100644
--- a/target/loongarch/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
@@ -3472,6 +3472,10 @@ TRANS(vsigncov_b, LSX, gvec_vvv, MO_8, do_vsigncov)
TRANS(vsigncov_h, LSX, gvec_vvv, MO_16, do_vsigncov)
TRANS(vsigncov_w, LSX, gvec_vvv, MO_32, do_vsigncov)
TRANS(vsigncov_d, LSX, gvec_vvv, MO_64, do_vsigncov)
+TRANS(xvsigncov_b, LASX, gvec_xxx, MO_8, do_vsigncov)
+TRANS(xvsigncov_h, LASX, gvec_xxx, MO_16, do_vsigncov)
+TRANS(xvsigncov_w, LASX, gvec_xxx, MO_32, do_vsigncov)
+TRANS(xvsigncov_d, LASX, gvec_xxx, MO_64, do_vsigncov)
TRANS(vmskltz_b, LSX, gen_vv, gen_helper_vmskltz_b)
TRANS(vmskltz_h, LSX, gen_vv, gen_helper_vmskltz_h)
--
2.39.1
- Re: [PATCH RESEND v5 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr, (continued)
[PATCH RESEND v5 45/57] target/loongarch: Implement xvfrstp, Song Gao, 2023/09/07
[PATCH RESEND v5 55/57] target/loongarch: Implement xvld xvst, Song Gao, 2023/09/07
[PATCH RESEND v5 50/57] target/loongarch: Implement xvbitsel xvset, Song Gao, 2023/09/07
[PATCH RESEND v5 57/57] target/loongarch: CPUCFG support LASX, Song Gao, 2023/09/07
[PATCH RESEND v5 53/57] target/loongarch: Implement xvpack xvpick xvilv{l/h}, Song Gao, 2023/09/07
[PATCH RESEND v5 52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve, Song Gao, 2023/09/07
[PATCH RESEND v5 31/57] target/loongarch: Implement xvsigncov,
Song Gao <=
[PATCH RESEND v5 24/57] target/loongarch: Implement xvmax/xvmin, Song Gao, 2023/09/07
[PATCH RESEND v5 20/57] target/loongarch: Implement xvaddw/xvsubw, Song Gao, 2023/09/07
[PATCH RESEND v5 22/57] target/loongarch: Implement xvabsd, Song Gao, 2023/09/07
[PATCH RESEND v5 26/57] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}, Song Gao, 2023/09/07
[PATCH RESEND v5 56/57] target/loongarch: Move simply DO_XX marcos togther, Song Gao, 2023/09/07
[PATCH RESEND v5 43/57] target/loongarch: Implement xvpcnt, Song Gao, 2023/09/07
[PATCH RESEND v5 44/57] target/loongarch: Implement xvbitclr xvbitset xvbitrev, Song Gao, 2023/09/07
[PATCH RESEND v5 54/57] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i, Song Gao, 2023/09/07