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[PULL v2 03/45] hw/char/riscv_htif: Fix the console syscall on big endia
From: |
Alistair Francis |
Subject: |
[PULL v2 03/45] hw/char/riscv_htif: Fix the console syscall on big endian hosts |
Date: |
Mon, 11 Sep 2023 16:42:38 +1000 |
From: Thomas Huth <thuth@redhat.com>
Values that have been read via cpu_physical_memory_read() from the
guest's memory have to be swapped in case the host endianess differs
from the guest.
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230721094720.902454-3-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/char/riscv_htif.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index f96df40124..40de6b8b77 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -30,6 +30,7 @@
#include "qemu/timer.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
+#include "exec/tswap.h"
#include "sysemu/dma.h"
#define RISCV_DEBUG_HTIF 0
@@ -209,11 +210,11 @@ static void htif_handle_tohost_write(HTIFState *s,
uint64_t val_written)
} else {
uint64_t syscall[8];
cpu_physical_memory_read(payload, syscall, sizeof(syscall));
- if (syscall[0] == PK_SYS_WRITE &&
- syscall[1] == HTIF_DEV_CONSOLE &&
- syscall[3] == HTIF_CONSOLE_CMD_PUTC) {
+ if (tswap64(syscall[0]) == PK_SYS_WRITE &&
+ tswap64(syscall[1]) == HTIF_DEV_CONSOLE &&
+ tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
uint8_t ch;
- cpu_physical_memory_read(syscall[2], &ch, 1);
+ cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
qemu_chr_fe_write(&s->chr, &ch, 1);
resp = 0x100 | (uint8_t)payload;
} else {
--
2.41.0
- [PULL v2 00/45] riscv-to-apply queue, Alistair Francis, 2023/09/11
- [PULL v2 01/45] target/riscv/cpu.c: do not run 'host' CPU with TCG, Alistair Francis, 2023/09/11
- [PULL v2 02/45] hw/char/riscv_htif: Fix printing of console characters on big endian hosts, Alistair Francis, 2023/09/11
- [PULL v2 03/45] hw/char/riscv_htif: Fix the console syscall on big endian hosts,
Alistair Francis <=
- [PULL v2 04/45] target/riscv/cpu.c: add zmmul isa string, Alistair Francis, 2023/09/11
- [PULL v2 05/45] target/riscv/cpu.c: add smepmp isa string, Alistair Francis, 2023/09/11
- [PULL v2 06/45] target/riscv: Fix page_check_range use in fault-only-first, Alistair Francis, 2023/09/11
- [PULL v2 07/45] target/riscv: Use existing lookup tables for MixColumns, Alistair Francis, 2023/09/11
- [PULL v2 08/45] target/riscv: Refactor some of the generic vector functionality, Alistair Francis, 2023/09/11
- [PULL v2 09/45] target/riscv: Refactor vector-vector translation macro, Alistair Francis, 2023/09/11
- [PULL v2 10/45] target/riscv: Remove redundant "cpu_vl == 0" checks, Alistair Francis, 2023/09/11
- [PULL v2 11/45] target/riscv: Add Zvbc ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 12/45] target/riscv: Move vector translation checks, Alistair Francis, 2023/09/11
- [PULL v2 13/45] target/riscv: Refactor translation of vector-widening instruction, Alistair Francis, 2023/09/11