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[PULL 08/30] target/arm: Update user-mode ID reg mask values
From: |
Peter Maydell |
Subject: |
[PULL 08/30] target/arm: Update user-mode ID reg mask values |
Date: |
Thu, 21 Sep 2023 18:36:58 +0100 |
For user-only mode we reveal a subset of the AArch64 ID registers
to the guest, to emulate the kernel's trap-and-emulate-ID-regs
handling. Update the feature bit masks to match upstream kernel
commit a48fa7efaf1161c1c.
None of these features are yet implemented by QEMU, so this
doesn't yet have a behavioural change, but implementation of
FEAT_MOPS and FEAT_HBC is imminent.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 11 ++++++++++-
tests/tcg/aarch64/sysregs.c | 4 ++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3b22596eabf..594985d7c8c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8621,11 +8621,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
R_ID_AA64ZFR0_F64MM_MASK },
{ .name = "ID_AA64SMFR0_EL1",
.exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
+ R_ID_AA64SMFR0_BI32I32_MASK |
R_ID_AA64SMFR0_B16F32_MASK |
R_ID_AA64SMFR0_F16F32_MASK |
R_ID_AA64SMFR0_I8I32_MASK |
+ R_ID_AA64SMFR0_F16F16_MASK |
+ R_ID_AA64SMFR0_B16B16_MASK |
+ R_ID_AA64SMFR0_I16I32_MASK |
R_ID_AA64SMFR0_F64F64_MASK |
R_ID_AA64SMFR0_I16I64_MASK |
+ R_ID_AA64SMFR0_SMEVER_MASK |
R_ID_AA64SMFR0_FA64_MASK },
{ .name = "ID_AA64MMFR0_EL1",
.exported_bits = R_ID_AA64MMFR0_ECV_MASK,
@@ -8676,7 +8681,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
R_ID_AA64ISAR2_RPRES_MASK |
R_ID_AA64ISAR2_GPA3_MASK |
- R_ID_AA64ISAR2_APA3_MASK },
+ R_ID_AA64ISAR2_APA3_MASK |
+ R_ID_AA64ISAR2_MOPS_MASK |
+ R_ID_AA64ISAR2_BC_MASK |
+ R_ID_AA64ISAR2_RPRFM_MASK |
+ R_ID_AA64ISAR2_CSSC_MASK },
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
.is_glob = true },
};
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
index d8eb06abcf2..f7a055f1d5f 100644
--- a/tests/tcg/aarch64/sysregs.c
+++ b/tests/tcg/aarch64/sysregs.c
@@ -126,7 +126,7 @@ int main(void)
*/
get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
- get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
+ get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(00ff,0000,00ff,ffff));
/* TGran4 & TGran64 as pegged to -1 */
get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
@@ -138,7 +138,7 @@ int main(void)
get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
get_cpu_reg_check_zero(id_aa64dfr1_el1);
get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,00ff,00ff));
- get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(80f1,00fd,0000,0000));
+ get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(8ff1,fcff,0000,0000));
get_cpu_reg_check_zero(id_aa64afr0_el1);
get_cpu_reg_check_zero(id_aa64afr1_el1);
--
2.34.1
- [PULL 00/30] target-arm queue, Peter Maydell, 2023/09/21
- [PULL 02/30] docs/devel/loads-stores: Fix git grep regexes, Peter Maydell, 2023/09/21
- [PULL 01/30] target/m68k: Add URL to semihosting spec, Peter Maydell, 2023/09/21
- [PULL 07/30] target/arm: Update AArch64 ID register field definitions, Peter Maydell, 2023/09/21
- [PULL 11/30] target/arm: Don't skip MTE checks for LDRT/STRT at EL0, Peter Maydell, 2023/09/21
- [PULL 09/30] target/arm: Implement FEAT_HBC, Peter Maydell, 2023/09/21
- [PULL 04/30] linux-user/elfload.c: Correct SME feature names reported in cpuinfo, Peter Maydell, 2023/09/21
- [PULL 03/30] hw/arm/boot: Set SCR_EL3.FGTEn when booting kernel, Peter Maydell, 2023/09/21
- [PULL 08/30] target/arm: Update user-mode ID reg mask values,
Peter Maydell <=
- [PULL 10/30] target/arm: Remove unused allocation_tag_mem() argument, Peter Maydell, 2023/09/21
- [PULL 12/30] target/arm: Implement FEAT_MOPS enable bits, Peter Maydell, 2023/09/21
- [PULL 14/30] target/arm: Define syndrome function for MOPS exceptions, Peter Maydell, 2023/09/21
- [PULL 17/30] target/arm: Implement the SET* instructions, Peter Maydell, 2023/09/21
- [PULL 05/30] linux-user/elfload.c: Add missing arm and arm64 hwcap values, Peter Maydell, 2023/09/21
- [PULL 19/30] target/arm: Implement the SETG* instructions, Peter Maydell, 2023/09/21
- [PULL 20/30] target/arm: Implement MTE tag-checking functions for FEAT_MOPS copies, Peter Maydell, 2023/09/21
- [PULL 16/30] target/arm: Implement MTE tag-checking functions for FEAT_MOPS, Peter Maydell, 2023/09/21
- [PULL 13/30] target/arm: Pass unpriv bool to get_a64_user_mem_index(), Peter Maydell, 2023/09/21
- [PULL 06/30] linux-user/elfload.c: Report previously missing arm32 hwcaps, Peter Maydell, 2023/09/21