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Re: [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base uni
From: |
Dave Jiang |
Subject: |
Re: [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS |
Date: |
Fri, 22 Sep 2023 13:59:42 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Betterbird/102.13.0 |
On 9/22/23 13:08, Michael Tokarev wrote:
> 04.09.2023 16:28, Jonathan Cameron:
>> From: Dave Jiang <dave.jiang@intel.com>
>>
>> According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth
>> Information Structure, if the "Entry Base Unit" is 1024 for BW and the
>> matrix entry has the value of 100, the BW is 100 GB/s. So the
>> entry_base_unit should be changed from 1000 to 1024 given the comment notes
>> it's 16GB/s for .latency_bandwidth.
>>
>> Fixes: 882877fc359d ("hw/pci-bridge/cxl-upstream: Add a CDAT table access
>> DOE")
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> ---
>> hw/pci-bridge/cxl_upstream.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c
>> index 9159f48a8c..2b9cf0cc97 100644
>> --- a/hw/pci-bridge/cxl_upstream.c
>> +++ b/hw/pci-bridge/cxl_upstream.c
>> @@ -262,7 +262,7 @@ static int build_cdat_table(CDATSubHeader ***cdat_table,
>> void *priv)
>> .length = sslbis_size,
>> },
>> .data_type = HMATLB_DATA_TYPE_ACCESS_BANDWIDTH,
>> - .entry_base_unit = 1000,
>> + .entry_base_unit = 1024,
>> },
>> };
>
> BTW, is this one stable-worthly? How it's been found, - due to some real
> issue or just by code review?
Code review. I was doing CXL CDAT parsing. So I guess I'm the first user. It's
small enough that it won't make much of a difference for the resulting computed
data. Mostly just correctness fixing.
>
> Thanks,
>
> /mjt
>
>
- [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup, Jonathan Cameron, 2023/09/04
- [PATCH 1/4] hw/cxl: Fix CFMW config memory leak, Jonathan Cameron, 2023/09/04
- [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS, Jonathan Cameron, 2023/09/04
- [PATCH 3/4] hw/cxl/cxl_device: Replace magic number in CXLError definition, Jonathan Cameron, 2023/09/04
- [PATCH 4/4] docs/cxl: Change to lowercase as others, Jonathan Cameron, 2023/09/04
- Re: [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup, Philippe Mathieu-Daudé, 2023/09/13
- Re: [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup, Michael Tokarev, 2023/09/13