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[PULL 00/21] tricore queue
From: |
Bastian Koppelmann |
Subject: |
[PULL 00/21] tricore queue |
Date: |
Wed, 27 Sep 2023 11:35:31 +0200 |
The following changes since commit 11a629d246e4e7785a6f0efb99bd15a32c04feda:
Merge tag 'pull-nbd-2023-09-25' of https://repo.or.cz/qemu/ericb into staging
(2023-09-26 09:04:23 -0400)
are available in the Git repository at:
https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230927
for you to fetch changes up to 32dd1f0b4bf5f38f37434b0c8fe6c8d86e093b2b:
target/tricore: Change effective address (ea) to target_ulong (2023-09-27
11:22:42 +0200)
----------------------------------------------------------------
- Add FTOU, CRCN, FTOHP, and HPTOF insns
- Add test for arithmetic TriCore insns
----------------------------------------------------------------
Bastian Koppelmann (21):
tests/tcg/tricore: Bump cpu to tc37x
target/tricore: Implement CRCN insn
target/tricore: Correctly handle FPU RM from PSW
target/tricore: Implement FTOU insn
target/tricore: Clarify special case for FTOUZ insn
target/tricore: Implement ftohp insn
target/tricore: Implement hptof insn
target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
target/tricore: Swap src and dst reg for RCRR_INSERT
target/tricore: Replace cpu_*_code with translator_*
target/tricore: Fix FTOUZ being ISA v1.3.1 up
tests/tcg/tricore: Extended and non-extened regs now match
hw/tricore: Log failing test in testdevice
tests/tcg: Reset result register after each test
tests/tcg/tricore: Add test for all arith insns up to addx
tests/tcg/tricore: Add test from 'and' to 'csub'
tests/tcg/tricore: Add test from 'dextr' to 'lt'
tests/tcg/tricore: Add test from 'max' to 'shas'
tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
target/tricore: Remove CSFRs from cpu.h
target/tricore: Change effective address (ea) to target_ulong
hw/tricore/tricore_testdevice.c | 4 +
target/tricore/cpu.h | 143 +--------------
target/tricore/fpu_helper.c | 111 ++++++++++++
target/tricore/helper.c | 19 +-
target/tricore/helper.h | 4 +
target/tricore/op_helper.c | 79 ++++++++-
target/tricore/translate.c | 56 ++++--
target/tricore/tricore-opcodes.h | 3 +
tests/tcg/tricore/Makefile.softmmu-target | 7 +-
tests/tcg/tricore/asm/macros.h | 190 +++++++++++++++++---
tests/tcg/tricore/asm/sas.py | 21 +++
tests/tcg/tricore/asm/test_arith.S | 280 ++++++++++++++++++++++++++++++
tests/tcg/tricore/asm/test_crcn.S | 9 +
tests/tcg/tricore/asm/test_ftohp.S | 14 ++
tests/tcg/tricore/asm/test_ftou.S | 12 ++
tests/tcg/tricore/asm/test_hptof.S | 12 ++
tests/tcg/tricore/asm/test_insert.S | 14 ++
17 files changed, 801 insertions(+), 177 deletions(-)
create mode 100644 tests/tcg/tricore/asm/sas.py
create mode 100644 tests/tcg/tricore/asm/test_arith.S
create mode 100644 tests/tcg/tricore/asm/test_crcn.S
create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
create mode 100644 tests/tcg/tricore/asm/test_ftou.S
create mode 100644 tests/tcg/tricore/asm/test_hptof.S
- [PULL 00/21] tricore queue,
Bastian Koppelmann <=
- [PULL 04/21] target/tricore: Implement FTOU insn, Bastian Koppelmann, 2023/09/27
- [PULL 05/21] target/tricore: Clarify special case for FTOUZ insn, Bastian Koppelmann, 2023/09/27
- [PULL 03/21] target/tricore: Correctly handle FPU RM from PSW, Bastian Koppelmann, 2023/09/27
- [PULL 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT, Bastian Koppelmann, 2023/09/27
- [PULL 02/21] target/tricore: Implement CRCN insn, Bastian Koppelmann, 2023/09/27
- [PULL 10/21] target/tricore: Replace cpu_*_code with translator_*, Bastian Koppelmann, 2023/09/27
- [PULL 12/21] tests/tcg/tricore: Extended and non-extened regs now match, Bastian Koppelmann, 2023/09/27
- [PULL 07/21] target/tricore: Implement hptof insn, Bastian Koppelmann, 2023/09/27
- [PULL 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0, Bastian Koppelmann, 2023/09/27
- [PULL 14/21] tests/tcg: Reset result register after each test, Bastian Koppelmann, 2023/09/27