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[PULL v2 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt'
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From: |
Bastian Koppelmann |
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Subject: |
[PULL v2 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt' |
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Date: |
Thu, 28 Sep 2023 10:52:59 +0200 |
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-7-kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 51 ++++++++++++++++++++++++++--
tests/tcg/tricore/asm/test_arith.S | 53 ++++++++++++++++++++++++++++++
2 files changed, 102 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 3000e15590..92f0f7b22b 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -34,6 +34,9 @@
#define EREG_RS2 %e2
#define EREG_RS2_LO %d2
#define EREG_RS2_HI %d3
+#define EREG_RS3 %e4
+#define EREG_RS3_LO %d4
+#define EREG_RS3_HI %d5
#define EREG_CALC_RESULT %e6
#define EREG_CALC_RESULT_LO %d6
#define EREG_CALC_RESULT_HI %d7
@@ -131,6 +134,26 @@ test_ ## num:
\
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
)
+#define TEST_D_DDDI(insn, num, result, rs1, rs2, rs3, imm) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ LI(DREG_RS3, rs3); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3, imm; \
+ )
+
+
+#define TEST_D_DDE(insn, num, result, rs1, rs2, rs3_lo, rs3_hi) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ LI(EREG_RS3_LO, rs3_lo); \
+ LI(EREG_RS3_HI, rs3_hi); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, EREG_RS3; \
+ )
+
#define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
LI(DREG_RS1, rs1); \
@@ -209,6 +232,12 @@ test_ ## num:
\
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
)
+#define TEST_E_DII(insn, num, res_lo, res_hi, rs1, imm1, imm2) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ insn EREG_CALC_RESULT, DREG_RS1, imm1, imm2; \
+ )
+
#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
@@ -247,7 +276,7 @@ test_ ## num:
\
insn EREG_CALC_RESULT, DREG_RS1; \
)
-#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
+#define TEST_E_ED(insn, num, res_lo, res_hi, rs1_lo, rs1_hi, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
LI(EREG_RS1_HI, rs1_hi); \
@@ -255,14 +284,32 @@ test_ ## num:
\
insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2; \
)
-#define TEST_E_IDI(insn, num, res_hi, res_lo, imm1, rs1, imm2) \
+#define TEST_E_IDI(insn, num, res_lo, res_hi, imm1, rs1, imm2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(DREG_RS1, rs1); \
rstv; \
insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2; \
)
+#define TEST_E_DD(insn, num, res_lo, res_hi, rs1, rs2) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ insn EREG_CALC_RESULT, DREG_RS1, DREG_RS2; \
+ )
+#define TEST_E_DDI(insn, num, res_lo, res_hi, rs1, rs2, imm) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ insn EREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
+ )
+
+#define TEST_E_III(insn, num, res_lo, res_hi, imm1, imm2, imm3) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ rstv; \
+ insn EREG_CALC_RESULT, imm1, imm2, imm3; \
+ )
/* Pass/Fail handling part */
#define TEST_PASSFAIL \
diff --git a/tests/tcg/tricore/asm/test_arith.S
b/tests/tcg/tricore/asm/test_arith.S
index ec87413777..68b6715cb9 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -84,5 +84,58 @@ _start:
TEST_D_DD(crc32l.w, 80, 0x1707579b, 0x87572060 ,0x8cdfa395 )
TEST_D_DDD(csub, 81, 0xf389f12f, 0xae9c7e04 ,0x63247211 ,0x6f9a80e2 )
TEST_D_DDD(csubn, 82, 0x2a7dd20d, 0xc39caf46 ,0x2a7dd20d ,0xa8ab6269 )
+ TEST_D_DDI(dextr, 83, 0x6b245592, 0x90d648ab ,0x2436a08d ,0x7 )
+ TEST_D_DDD(dextr, 84, 0x4e9d8172, 0x6b8c6274 ,0xec0b9772 ,0x7ab0d8f5 )
+ TEST_E_ED(dvadj, 85, 0xfb793929 ,0xf15f4ecc, 0xfb793928 ,0xf15f4ecc
,0x5de9a7b4 )
+ TEST_E_DD(dvinit, 86, 0xbbd99367 ,0xffffffff, 0xbbd99367 ,0xa248dff9 )
+ TEST_E_DD(dvinit.b, 87, 0x58ffffff ,0x1f3f20, 0x1f3f2058 ,0xfed6c3ec )
+ TEST_E_DD(dvinit.bu, 88, 0xa000000 ,0x8bbf54, 0x8bbf540a ,0xa0bcfdde )
+ TEST_E_DD(dvinit.h, 89, 0xfe59ffff ,0x6d07, 0x6d07fe59 ,0xe4a6e12c )
+ TEST_E_DD(dvinit.hu, 90, 0x8e5d0000 ,0x37bd, 0x37bd8e5d ,0x38c0be4c )
+ TEST_E_DD(dvinit.u, 91, 0x613ca148 ,0x0, 0x613ca148 ,0x79e89e70 )
+ TEST_E_ED(dvstep.u, 92, 0x90388180 ,0x356c3f47, 0x47903881 ,0xd5b131ef
,0xa8f78b60 )
+ TEST_D_DI(eq, 93, 0x0, 0x22cf24bc ,0x3c )
+ TEST_D_DD(eq, 94, 0x0, 0x1b220983 ,0x60d6182 )
+ TEST_D15_DI(eq, 95, 0x0, 0x66b1313e ,0x1 )
+ TEST_D15_DD(eq, 96, 0x0, 0x3a6b6484 ,0xe1bdc794 )
+ TEST_D_DD(eq.b, 97, 0x0, 0x1413e6a2 ,0x8237ab11 )
+ TEST_D_DD(eq.h, 98, 0x0, 0xc2d2cdd3 ,0xfd8576be )
+ TEST_D_DD(eq.w, 99, 0x0, 0x1b6f66d7 ,0x738035d1 )
+ TEST_D_DI(eqany.b, 100, 0x0, 0xfb630c56 ,0x9f )
+ TEST_D_DD(eqany.b, 101, 0x0, 0x5cdbbb44 ,0xf7911917 )
+ TEST_D_DI(eqany.h, 102, 0x0, 0xd31af4d0 ,0xc )
+ TEST_D_DD(eqany.h, 103, 0x0, 0x6bd800e2 ,0x8bea6be7 )
+ TEST_D_DI(ge, 104, 0x1, 0x3d3d0f67 ,0x6d )
+ TEST_D_DD(ge, 105, 0x1, 0x7238ba92 ,0x3d6d3327 )
+ TEST_D_DI(ge.u, 106, 0x1, 0xc34402cb ,0xf2 )
+ TEST_D_DD(ge.u, 107, 0x1, 0xf44ec751 ,0x42f3f12d )
+ TEST_E_III(imask, 108, 0x1c0 ,0x1c0, 0x7 ,0x6 ,0x3 )
+ TEST_E_IDI(imask, 109, 0x1 ,0x7f, 0x1 ,0xa7390380 ,0x7 )
+ TEST_E_DII(imask, 110, 0x3fdaaa80 ,0x1fc0, 0x14ff6aaa ,0x6 ,0x7 )
+ TEST_E_DDI(imask, 111, 0xfc8a94c0 ,0x1f0, 0xafc8a94c ,0x37ceafe4 ,0x5 )
+ TEST_D_DIDI(ins.t, 112, 0x3991c755, 0x3991c755 ,0x2 ,0xa9b171ef ,0x4 )
+ TEST_D_DIII(insert, 113, 0x9997e4d7, 0x9997e497 ,0x6 ,0x5 ,0x2 )
+ TEST_D_DIE(insert, 114, 0x71169ed, 0xaf1169ed ,0x1 ,0xf5abe69a ,0xaef09348
)
+ TEST_D_DIDI(insert, 115, 0x8a228466, 0x8a2284e6 ,0x5 ,0x2c808a7f ,0x2 )
+ TEST_D_DDII(insert, 116, 0xeffef7ec, 0xeffef7e8 ,0xaa92b4ce ,0x1 ,0x3 )
+ TEST_D_DDE(insert, 117, 0x7948cba3, 0x818b7ba3 ,0x70bca465 ,0x47ede909
,0xbf4f8afe )
+ TEST_D_DDDI(insert, 118, 0x5e974875, 0x5b774875 ,0x27f33374 ,0x4b417135
,0x7 )
+ TEST_D_DIDI(insn.t, 119, 0xcbbe860a, 0xcbbe860a ,0x4 ,0xd2f483d9 ,0x3 )
+ TEST_E_ED(ixmax, 120, 0x48ef48f1 ,0x6e7e, 0x687e48ef ,0x9afdc6c8
,0xbd066e7e )
+ TEST_E_ED(ixmax.u, 121, 0xac97ac98 ,0xd968, 0x67b7ac96 ,0x55371874
,0xd968399e )
+ TEST_E_ED(ixmin, 122, 0x957f9580 ,0xa9de, 0x8ed957e ,0x9519d426
,0xa9de69e1 )
+ TEST_E_ED(ixmin.u, 123, 0xde48de4a ,0x3660, 0x3dc4de48 ,0x1e5a559d
,0xdbc53660 )
+ TEST_D_DI(lt, 124, 0x1, 0xf156e5c0 ,0x40 )
+ TEST_D_DD(lt, 125, 0x0, 0x51c83765 ,0x1aa7292 )
+ TEST_D15_DI(lt, 126, 0x0, 0x31163fc9 ,0x5 )
+ TEST_D15_DD(lt, 127, 0x1, 0xf9e43e50 ,0x22a3f8d5 )
+ TEST_D_DD(lt.b, 128, 0xff0000, 0x4a374b04 ,0x4869ba92 )
+ TEST_D_DD(lt.bu, 129, 0xff00, 0x4c5bb0c7 ,0x4c3bd2a3 )
+ TEST_D_DD(lt.h, 130, 0xffff0000, 0x326e5bdc ,0x33e03761 )
+ TEST_D_DD(lt.hu, 131, 0x0, 0xf53b8e9b ,0x53cc7810 )
+ TEST_D_DI(lt.u, 132, 0x0, 0xf1f78a54 ,0x4d )
+ TEST_D_DD(lt.u, 133, 0x1, 0x10fedada ,0x265af026 )
+ TEST_D_DD(lt.w, 134, 0xffffffff, 0xbc8a0b22 ,0x3dd6d1a2 )
+ TEST_D_DD(lt.wu, 135, 0x0, 0xcc92a312 ,0x133c8a9d )
TEST_PASSFAIL
--
2.42.0
- [PULL v2 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0, (continued)
- [PULL v2 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0, Bastian Koppelmann, 2023/09/28
- [PULL v2 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT, Bastian Koppelmann, 2023/09/28
- [PULL v2 10/21] target/tricore: Replace cpu_*_code with translator_*, Bastian Koppelmann, 2023/09/28
- [PULL v2 11/21] target/tricore: Fix FTOUZ being ISA v1.3.1 up, Bastian Koppelmann, 2023/09/28
- [PULL v2 12/21] tests/tcg/tricore: Extended and non-extened regs now match, Bastian Koppelmann, 2023/09/28
- [PULL v2 13/21] hw/tricore: Log failing test in testdevice, Bastian Koppelmann, 2023/09/28
- [PULL v2 14/21] tests/tcg: Reset result register after each test, Bastian Koppelmann, 2023/09/28
- [PULL v2 15/21] tests/tcg/tricore: Add test for all arith insns up to addx, Bastian Koppelmann, 2023/09/28
- [PULL v2 16/21] tests/tcg/tricore: Add test from 'and' to 'csub', Bastian Koppelmann, 2023/09/28
- [PULL v2 20/21] target/tricore: Remove CSFRs from cpu.h, Bastian Koppelmann, 2023/09/28
- [PULL v2 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt',
Bastian Koppelmann <=
- [PULL v2 18/21] tests/tcg/tricore: Add test from 'max' to 'shas', Bastian Koppelmann, 2023/09/28
- [PULL v2 19/21] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t', Bastian Koppelmann, 2023/09/28
- [PULL v2 21/21] target/tricore: Change effective address (ea) to target_ulong, Bastian Koppelmann, 2023/09/28
- Re: [PULL v2 00/21] tricore queue, Stefan Hajnoczi, 2023/09/28