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[PATCH for-9.0 1/4] vga: merge conditionals on shift control register
From: |
Paolo Bonzini |
Subject: |
[PATCH for-9.0 1/4] vga: merge conditionals on shift control register |
Date: |
Tue, 2 Apr 2024 13:34:03 +0200 |
There are two sets of conditionals using the shift control bits: one to
verify the palette and adjust disp_width, one to compute the "v" and
"bits" variables. Merge them into one, with the extra benefit that
we now have the "bits" value available early and can use it to
compute region_end.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/display/vga.c | 89 +++++++++++++++++++++++-------------------------
1 file changed, 42 insertions(+), 47 deletions(-)
diff --git a/hw/display/vga.c b/hw/display/vga.c
index bc5b83421bf..4795a0012e2 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -1546,12 +1546,54 @@ static void vga_draw_graphic(VGACommonState *s, int
full_update)
}
if (shift_control == 0) {
+ full_update |= update_palette16(s);
if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
disp_width <<= 1;
+ v = VGA_DRAW_LINE4D2;
+ } else {
+ v = VGA_DRAW_LINE4;
}
+ bits = 4;
+
} else if (shift_control == 1) {
+ full_update |= update_palette16(s);
if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
disp_width <<= 1;
+ v = VGA_DRAW_LINE2D2;
+ } else {
+ v = VGA_DRAW_LINE2;
+ }
+ bits = 4;
+
+ } else {
+ switch (depth) {
+ default:
+ case 0:
+ full_update |= update_palette256(s);
+ v = VGA_DRAW_LINE8D2;
+ bits = 4;
+ break;
+ case 8:
+ full_update |= update_palette256(s);
+ v = VGA_DRAW_LINE8;
+ bits = 8;
+ break;
+ case 15:
+ v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
+ bits = 16;
+ break;
+ case 16:
+ v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
+ bits = 16;
+ break;
+ case 24:
+ v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
+ bits = 24;
+ break;
+ case 32:
+ v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
+ bits = 32;
+ break;
}
}
@@ -1607,53 +1649,6 @@ static void vga_draw_graphic(VGACommonState *s, int
full_update)
}
}
- if (shift_control == 0) {
- full_update |= update_palette16(s);
- if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
- v = VGA_DRAW_LINE4D2;
- } else {
- v = VGA_DRAW_LINE4;
- }
- bits = 4;
- } else if (shift_control == 1) {
- full_update |= update_palette16(s);
- if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
- v = VGA_DRAW_LINE2D2;
- } else {
- v = VGA_DRAW_LINE2;
- }
- bits = 4;
- } else {
- switch(s->get_bpp(s)) {
- default:
- case 0:
- full_update |= update_palette256(s);
- v = VGA_DRAW_LINE8D2;
- bits = 4;
- break;
- case 8:
- full_update |= update_palette256(s);
- v = VGA_DRAW_LINE8;
- bits = 8;
- break;
- case 15:
- v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
- bits = 16;
- break;
- case 16:
- v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
- bits = 16;
- break;
- case 24:
- v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
- bits = 24;
- break;
- case 32:
- v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
- bits = 32;
- break;
- }
- }
vga_draw_line = vga_draw_line_table[v];
if (!is_buffer_shared(surface) && s->cursor_invalidate) {
--
2.44.0
- [PATCH for-9.0 0/4] vga: fix assertion failure with 4- and 16-color modes, Paolo Bonzini, 2024/04/02
- [PATCH for-9.0 1/4] vga: merge conditionals on shift control register,
Paolo Bonzini <=
- [PATCH for-9.0 2/4] vga: move computation of dirty memory region later, Paolo Bonzini, 2024/04/02
- [PATCH for-9.0 4/4] vga: do not treat horiz pel panning value of 8 as "enabled", Paolo Bonzini, 2024/04/02
- [PATCH for-9.0 3/4] vga: adjust dirty memory region if pel panning is active, Paolo Bonzini, 2024/04/02
- [PATCH for-9.1 5/4] vga: optimize computation of dirty memory region, Paolo Bonzini, 2024/04/02
- [PATCH for-9.1 6/4] vga: move dirty memory region code together, Paolo Bonzini, 2024/04/02