Hi peter;
much, much appreciate your explanation!
> ..but the host doesn't have one, we arrange to pause execution of all the other guest vCPU threads,
===>yes, i somehow a little bit of guess such like that, but when try to find some code in qemu to prove the guess, i found i was lost and exausted in the ocean of the code and complex logic of qeumu.
because in my thougth, it may be do the sync in user pthread level, so i grep the "pthread" "mutex", "condtion",... and so on, but did not find any position to prove this thought.
so, can you offer me the demo code position of do the sync like "pause execution of all the other guest vCPU threads,", to make the atomic operations meet the sematics?
thank you!
BRs
zlcao.
At 2024-04-09 18:10:42, "Peter Maydell" <peter.maydell@linaro.org> wrote:
>On Tue, 9 Apr 2024 at 10:58, tugouxp <13824125580@163.com> wrote:
>> How does the qemu emulate the target that support "atomic" ISA, such as riscv "amo" instruction on host machine that does NOT support atomic instructions ?
>> is this scenario happends?
>
>All hosts that can run QEMU support at least some atomic instructions.
>Where possible we use the host atomic operations to provide the
>necessary atomicity guarantees that a guest instruction must have.
>For cases where we can't do that (eg where the guest needs an atomic
>16-byte store but the host doesn't have one), we arrange to pause
>execution of all the other guest vCPU threads, do the thing that must
>be atomic, and then let everything resume.
>
>thanks
>-- PMM