[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 16/20] target/microblaze: Use insn_start from DisasContextBase
From: |
Richard Henderson |
Subject: |
[PULL v2 16/20] target/microblaze: Use insn_start from DisasContextBase |
Date: |
Tue, 9 Apr 2024 09:35:59 -1000 |
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/translate.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 4e52ef32db..fc451befae 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -62,9 +62,6 @@ typedef struct DisasContext {
DisasContextBase base;
const MicroBlazeCPUConfig *cfg;
- /* TCG op of the current insn_start. */
- TCGOp *insn_start;
-
TCGv_i32 r0;
bool r0_set;
@@ -699,14 +696,14 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int
ra, int rb)
static void record_unaligned_ess(DisasContext *dc, int rd,
MemOp size, bool store)
{
- uint32_t iflags = tcg_get_insn_start_param(dc->insn_start, 1);
+ uint32_t iflags = tcg_get_insn_start_param(dc->base.insn_start, 1);
iflags |= ESR_ESS_FLAG;
iflags |= rd << 5;
iflags |= store * ESR_S;
iflags |= (size == MO_32) * ESR_W;
- tcg_set_insn_start_param(dc->insn_start, 1, iflags);
+ tcg_set_insn_start_param(dc->base.insn_start, 1, iflags);
}
#endif
@@ -1624,7 +1621,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb,
CPUState *cs)
DisasContext *dc = container_of(dcb, DisasContext, base);
tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);
- dc->insn_start = tcg_last_op();
}
static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
--
2.34.1
- [PULL v2 06/20] target/sh4: Merge mach and macl into a union, (continued)
- [PULL v2 06/20] target/sh4: Merge mach and macl into a union, Richard Henderson, 2024/04/09
- [PULL v2 07/20] target/sh4: Fix mac.l with saturation enabled, Richard Henderson, 2024/04/09
- [PULL v2 08/20] target/sh4: Fix mac.w with saturation enabled, Richard Henderson, 2024/04/09
- [PULL v2 09/20] target/sh4: add missing CHECK_NOT_DELAY_SLOT, Richard Henderson, 2024/04/09
- [PULL v2 10/20] target/m68k: Map FPU exceptions to FPSR register, Richard Henderson, 2024/04/09
- [PULL v2 11/20] tcg: Add TCGContext.emit_before_op, Richard Henderson, 2024/04/09
- [PULL v2 12/20] accel/tcg: Add insn_start to DisasContextBase, Richard Henderson, 2024/04/09
- [PULL v2 14/20] target/hppa: Use insn_start from DisasContextBase, Richard Henderson, 2024/04/09
- [PULL v2 13/20] target/arm: Use insn_start from DisasContextBase, Richard Henderson, 2024/04/09
- [PULL v2 15/20] target/i386: Preserve DisasContextBase.insn_start across rewind, Richard Henderson, 2024/04/09
- [PULL v2 16/20] target/microblaze: Use insn_start from DisasContextBase,
Richard Henderson <=
- [PULL v2 17/20] target/riscv: Use insn_start from DisasContextBase, Richard Henderson, 2024/04/09
- [PULL v2 18/20] target/s390x: Use insn_start from DisasContextBase, Richard Henderson, 2024/04/09
- [PULL v2 19/20] accel/tcg: Improve can_do_io management, Richard Henderson, 2024/04/09
- [PULL v2 20/20] linux-user: Preserve unswapped siginfo_t for strace, Richard Henderson, 2024/04/09
- Re: [PULL v2 00/20] misc patch queue, Peter Maydell, 2024/04/10
- Re: [PULL v2 00/20] misc patch queue, Michael Tokarev, 2024/04/10