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[PULL 24/63] kvm: add support for guest physical bits
From: |
Paolo Bonzini |
Subject: |
[PULL 24/63] kvm: add support for guest physical bits |
Date: |
Tue, 23 Apr 2024 17:09:12 +0200 |
From: Gerd Hoffmann <kraxel@redhat.com>
Query kvm for supported guest physical address bits, in cpuid
function 80000008, eax[23:16]. Usually this is identical to host
physical address bits. With NPT or EPT being used this might be
restricted to 48 (max 4-level paging address space size) even if
the host cpu supports more physical address bits.
When set pass this to the guest, using cpuid too. Guest firmware
can use this to figure how big the usable guest physical address
space is, so PCI bar mapping are actually reachable.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-ID: <20240318155336.156197-2-kraxel@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/kvm/kvm-cpu.c | 50 ++++++++++++++++++++++++++++++++-------
1 file changed, 42 insertions(+), 8 deletions(-)
diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
index 9c791b7b052..f76972e47e6 100644
--- a/target/i386/kvm/kvm-cpu.c
+++ b/target/i386/kvm/kvm-cpu.c
@@ -18,10 +18,32 @@
#include "kvm_i386.h"
#include "hw/core/accel-cpu.h"
+static void kvm_set_guest_phys_bits(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ uint32_t eax, guest_phys_bits;
+
+ eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x80000008, 0, R_EAX);
+ guest_phys_bits = (eax >> 16) & 0xff;
+ if (!guest_phys_bits) {
+ return;
+ }
+ cpu->guest_phys_bits = guest_phys_bits;
+ if (cpu->guest_phys_bits > cpu->phys_bits) {
+ cpu->guest_phys_bits = cpu->phys_bits;
+ }
+
+ if (cpu->host_phys_bits && cpu->host_phys_bits_limit &&
+ cpu->guest_phys_bits > cpu->host_phys_bits_limit) {
+ cpu->guest_phys_bits = cpu->host_phys_bits_limit;
+ }
+}
+
static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
+ bool ret;
/*
* The realize order is important, since x86_cpu_realize() checks if
@@ -32,13 +54,15 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
*
* realize order:
*
- * x86_cpu_realize():
- * -> x86_cpu_expand_features()
- * -> cpu_exec_realizefn():
- * -> accel_cpu_common_realize()
- * kvm_cpu_realizefn() -> host_cpu_realizefn()
- * -> cpu_common_realizefn()
- * -> check/update ucode_rev, phys_bits, mwait
+ * x86_cpu_realizefn():
+ * x86_cpu_expand_features()
+ * cpu_exec_realizefn():
+ * accel_cpu_common_realize()
+ * kvm_cpu_realizefn()
+ * host_cpu_realizefn()
+ * kvm_set_guest_phys_bits()
+ * check/update ucode_rev, phys_bits, guest_phys_bits, mwait
+ * cpu_common_realizefn() (via xcc->parent_realize)
*/
if (cpu->max_features) {
if (enable_cpu_pm && kvm_has_waitpkg()) {
@@ -50,7 +74,17 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
MSR_IA32_UCODE_REV);
}
}
- return host_cpu_realizefn(cs, errp);
+ ret = host_cpu_realizefn(cs, errp);
+ if (!ret) {
+ return ret;
+ }
+
+ if ((env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) &&
+ cpu->guest_phys_bits == -1) {
+ kvm_set_guest_phys_bits(cs);
+ }
+
+ return true;
}
static bool lmce_supported(void)
--
2.44.0
- [PULL 23/63] target/i386: add guest-phys-bits cpu property, (continued)
- [PULL 23/63] target/i386: add guest-phys-bits cpu property, Paolo Bonzini, 2024/04/23
- [PULL 25/63] i386/kvm: Move architectural CPUID leaf generation to separate helper, Paolo Bonzini, 2024/04/23
- [PULL 30/63] q35: Introduce smm_ranges property for q35-pci-host, Paolo Bonzini, 2024/04/23
- [PULL 39/63] runstate: skip initial CPU reset if reset is not actually possible, Paolo Bonzini, 2024/04/23
- [PULL 48/63] kvm: Introduce support for memory_attributes, Paolo Bonzini, 2024/04/23
- [PULL 38/63] linux-headers: update to current kvm/next, Paolo Bonzini, 2024/04/23
- [PULL 53/63] RAMBlock: make guest_memfd require uncoordinated discard, Paolo Bonzini, 2024/04/23
- [PULL 55/63] kvm: handle KVM_EXIT_MEMORY_FAULT, Paolo Bonzini, 2024/04/23
- [PULL 54/63] physmem: Introduce ram_block_discard_guest_memfd_range(), Paolo Bonzini, 2024/04/23
- [PULL 24/63] kvm: add support for guest physical bits,
Paolo Bonzini <=
- [PULL 60/63] target/i386/cpu: Merge the warning and error messages for AMD HT check, Paolo Bonzini, 2024/04/23
- [PULL 63/63] target/i386/translate.c: always write 32-bits for SGDT and SIDT, Paolo Bonzini, 2024/04/23
- [PULL 42/63] target/i386: introduce x86-confidential-guest, Paolo Bonzini, 2024/04/23
- [PULL 15/63] colo: move stubs out of stubs/, Paolo Bonzini, 2024/04/23
- Re: [PULL 00/63] First batch of i386 and build system patch for QEMU 9.1, Richard Henderson, 2024/04/24