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[PULL 13/37] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device
From: |
Peter Maydell |
Subject: |
[PULL 13/37] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device |
Date: |
Thu, 25 Apr 2024 11:39:34 +0100 |
From: Jinjie Ruan <ruanjinjie@huawei.com>
Add a property has-nmi to the GICv3 device, and use this to set
the NMI bit in the GICD_TYPER register. This isn't visible to
guests yet because the property defaults to false and we won't
set it in the board code until we've landed all of the changes
needed to implement FEAT_GICV3_NMI.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/gicv3_internal.h | 1 +
include/hw/intc/arm_gicv3_common.h | 1 +
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
4 files changed, 5 insertions(+)
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 29d5cdc1b69..8f4ebed2f42 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,7 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_NMI_SHIFT 9
#define GICD_TYPER_LPIS_SHIFT 17
/* 16 bits EventId */
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index 7324c7d983f..4358c5319c1 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -249,6 +249,7 @@ struct GICv3State {
uint32_t num_irq;
uint32_t revision;
bool lpi_enable;
+ bool nmi_support;
bool security_extn;
bool force_8bit_prio;
bool irq_reset_nonsecure;
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index c52f060026a..2d2cea6858a 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -569,6 +569,7 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
+ DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
/*
* Compatibility property: force 8 bits of physical priority, even
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index 35e850685c0..22ddc0d6661 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -389,6 +389,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
* by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
+ * NMI = 1 if Non-maskable interrupt property is supported
* CPUNumber == 0 since for us ARE is always 1
* ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
*/
@@ -402,6 +403,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
bool dvis = s->revision >= 4;
*data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) |
+ (s->nmi_support << GICD_TYPER_NMI_SHIFT) |
(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
(0xf << 19) | itlinesnumber;
return true;
--
2.34.1
- [PULL 00/37] target-arm queue, Peter Maydell, 2024/04/25
- [PULL 02/37] target/arm: Add PSTATE.ALLINT, Peter Maydell, 2024/04/25
- [PULL 03/37] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Peter Maydell, 2024/04/25
- [PULL 04/37] target/arm: Implement ALLINT MSR (immediate), Peter Maydell, 2024/04/25
- [PULL 01/37] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Peter Maydell, 2024/04/25
- [PULL 10/37] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Peter Maydell, 2024/04/25
- [PULL 05/37] target/arm: Support MSR access to ALLINT, Peter Maydell, 2024/04/25
- [PULL 07/37] target/arm: Add support for NMI in arm_phys_excp_target_el(), Peter Maydell, 2024/04/25
- [PULL 06/37] target/arm: Add support for Non-maskable Interrupt, Peter Maydell, 2024/04/25
- [PULL 08/37] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, Peter Maydell, 2024/04/25
- [PULL 13/37] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device,
Peter Maydell <=
- [PULL 14/37] hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3, Peter Maydell, 2024/04/25
- [PULL 15/37] hw/intc/arm_gicv3: Add irq non-maskable property, Peter Maydell, 2024/04/25
- [PULL 19/37] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Peter Maydell, 2024/04/25
- [PULL 21/37] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Peter Maydell, 2024/04/25
- [PULL 26/37] linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code, Peter Maydell, 2024/04/25
- [PULL 29/37] scripts/coccinelle: New script to add ResetType to hold and exit phases, Peter Maydell, 2024/04/25
- [PULL 18/37] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Peter Maydell, 2024/04/25
- [PULL 33/37] hw/char: Implement STM32L4x5 USART skeleton, Peter Maydell, 2024/04/25
- [PULL 12/37] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2024/04/25
- [PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception, Peter Maydell, 2024/04/25