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[PULL 16/37] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0
From: |
Peter Maydell |
Subject: |
[PULL 16/37] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 |
Date: |
Thu, 25 Apr 2024 11:39:37 +0100 |
From: Jinjie Ruan <ruanjinjie@huawei.com>
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/gicv3_internal.h | 1 +
hw/intc/arm_gicv3_redist.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 8f4ebed2f42..21697ecf391 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -110,6 +110,7 @@
#define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04)
#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
+#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80)
/* VLPI redistributor registers, offsets from VLPI_base */
#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 8153525849a..ed1f9d1e444 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq)
return extract32(cs->gicr_nsacr, irq * 2, 2);
}
+static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
+ uint32_t *reg, uint32_t val)
+{
+ /* Helper routine to implement writing to a "set" register */
+ val &= mask_group(cs, attrs);
+ *reg = val;
+ gicv3_redist_update(cs);
+}
+
static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
uint32_t *reg, uint32_t val)
{
@@ -406,6 +415,10 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr
offset,
*data = value;
return MEMTX_OK;
}
+ case GICR_INMIR0:
+ *data = cs->gic->nmi_support ?
+ gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0;
+ return MEMTX_OK;
case GICR_ICFGR0:
case GICR_ICFGR1:
{
@@ -555,6 +568,12 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
gicv3_redist_update(cs);
return MEMTX_OK;
}
+ case GICR_INMIR0:
+ if (cs->gic->nmi_support) {
+ gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value);
+ }
+ return MEMTX_OK;
+
case GICR_ICFGR0:
/* Register is all RAZ/WI or RAO/WI bits */
return MEMTX_OK;
--
2.34.1
- [PULL 15/37] hw/intc/arm_gicv3: Add irq non-maskable property, (continued)
- [PULL 15/37] hw/intc/arm_gicv3: Add irq non-maskable property, Peter Maydell, 2024/04/25
- [PULL 19/37] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Peter Maydell, 2024/04/25
- [PULL 21/37] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Peter Maydell, 2024/04/25
- [PULL 26/37] linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code, Peter Maydell, 2024/04/25
- [PULL 29/37] scripts/coccinelle: New script to add ResetType to hold and exit phases, Peter Maydell, 2024/04/25
- [PULL 18/37] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Peter Maydell, 2024/04/25
- [PULL 33/37] hw/char: Implement STM32L4x5 USART skeleton, Peter Maydell, 2024/04/25
- [PULL 12/37] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2024/04/25
- [PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception, Peter Maydell, 2024/04/25
- [PULL 11/37] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Peter Maydell, 2024/04/25
- [PULL 16/37] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0,
Peter Maydell <=
- [PULL 17/37] hw/intc/arm_gicv3: Implement GICD_INMIR, Peter Maydell, 2024/04/25
- [PULL 20/37] hw/intc/arm_gicv3: Implement NMI interrupt priority, Peter Maydell, 2024/04/25
- [PULL 22/37] hw/intc/arm_gicv3: Report the VINMI interrupt, Peter Maydell, 2024/04/25
- [PULL 23/37] target/arm: Add FEAT_NMI to max, Peter Maydell, 2024/04/25
- [PULL 25/37] hw/dma: avoid apparent overflow in soc_dma_set_request, Peter Maydell, 2024/04/25
- [PULL 24/37] hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI, Peter Maydell, 2024/04/25
- [PULL 27/37] hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr, Peter Maydell, 2024/04/25
- [PULL 28/37] allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset, Peter Maydell, 2024/04/25
- [PULL 32/37] reset: Add RESET_TYPE_SNAPSHOT_LOAD, Peter Maydell, 2024/04/25
- [PULL 34/37] hw/char/stm32l4x5_usart: Enable serial read and write, Peter Maydell, 2024/04/25