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[PULL 06/21] target/arm: Enable FEAT_ETS2 for -cpu max
From: |
Peter Maydell |
Subject: |
[PULL 06/21] target/arm: Enable FEAT_ETS2 for -cpu max |
Date: |
Tue, 30 Apr 2024 17:48:27 +0100 |
FEAT_ETS2 is a tighter set of guarantees about memory ordering
involving translation table walks than the old FEAT_ETS; FEAT_ETS has
been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
now gives no greater guarantees than ETS == 0.
FEAT_ETS2 requires:
* the virtual address of a load or store that appears in program
order after a DSB cannot be translated until after the DSB
completes (section B2.10.9)
* TLB maintenance operations that only affect translations without
execute permission are guaranteed complete after a DSB
(R_BLDZX)
* if a memory access RW2 is ordered-before memory access RW2,
then RW1 is also ordered-before any translation table walk
generated by RW2 that generates a Translation, Address size
or Access flag fault (R_NNFPF, I_CLGHP)
As with FEAT_ETS, QEMU is already compliant, because we do not
reorder translation table walk memory accesses relative to other
memory accesses, and we always guarantee to have finished TLB
maintenance as soon as the TLB op is done.
Update the documentation to list FEAT_ETS2 instead of the
no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
---
docs/system/arm/emulation.rst | 2 +-
target/arm/tcg/cpu32.c | 2 +-
target/arm/tcg/cpu64.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index d70b66f7530..307539cff91 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -50,7 +50,7 @@ the following architecture extensions:
- FEAT_EL2 (Support for execution at EL2)
- FEAT_EL3 (Support for execution at EL3)
- FEAT_EPAC (Enhanced pointer authentication)
-- FEAT_ETS (Enhanced Translation Synchronization)
+- FEAT_ETS2 (Enhanced Translation Synchronization)
- FEAT_EVT (Enhanced Virtualization Traps)
- FEAT_F32MM (Single-precision Matrix Multiplication)
- FEAT_F64MM (Double-precision Matrix Multiplication)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index de8f2be9416..b5a60682fa6 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -67,7 +67,7 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_mmfr4 = t;
t = cpu->isar.id_mmfr5;
- t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
+ t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
cpu->isar.id_mmfr5 = t;
t = cpu->isar.id_pfr0;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 8ad05c53e8d..ebb585afd85 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1196,7 +1196,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
- t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
+ t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */
t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */
cpu->isar.id_aa64mmfr1 = t;
--
2.34.1
- [PULL 00/21] target-arm queue, Peter Maydell, 2024/04/30
- [PULL 02/21] hvf: arm: Remove PL1_WRITE_MASK, Peter Maydell, 2024/04/30
- [PULL 03/21] target/arm: Restrict translation disabled alignment check to VMSA, Peter Maydell, 2024/04/30
- [PULL 06/21] target/arm: Enable FEAT_ETS2 for -cpu max,
Peter Maydell <=
- [PULL 08/21] target/arm: Enable FEAT_Spec_FPACC for -cpu max, Peter Maydell, 2024/04/30
- [PULL 05/21] target/arm: Enable FEAT_CSV2_3 for -cpu max, Peter Maydell, 2024/04/30
- [PULL 01/21] hw/core/clock: allow clock_propagate on child clocks, Peter Maydell, 2024/04/30
- [PULL 04/21] docs/system/arm/emulation.rst: Add missing implemented features, Peter Maydell, 2024/04/30
- [PULL 09/21] tests/avocado: update sunxi kernel from armbian to 6.6.16, Peter Maydell, 2024/04/30
- [PULL 11/21] hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz, Peter Maydell, 2024/04/30
- [PULL 12/21] hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property, Peter Maydell, 2024/04/30
- [PULL 10/21] target/arm: Refactor default generic timer frequency handling, Peter Maydell, 2024/04/30
- [PULL 07/21] target/arm: Implement ID_AA64MMFR3_EL1, Peter Maydell, 2024/04/30
- [PULL 16/21] hw/arm/npcm7xx: Store derivative OTP fuse key in little endian, Peter Maydell, 2024/04/30