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[PULL 14/25] target/i386: fix bad sorting of entries in the 0F table
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From: |
Paolo Bonzini |
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Subject: |
[PULL 14/25] target/i386: fix bad sorting of entries in the 0F table |
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Date: |
Tue, 11 Jun 2024 16:25:12 +0200 |
Aesthetic change only.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 93 ++++++++++++++++----------------
1 file changed, 46 insertions(+), 47 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 4c567911f41..4e745f10dd8 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -1006,14 +1006,6 @@ static void decode_MOV_CR_DR(DisasContext *s,
CPUX86State *env, X86OpEntry *entr
}
static const X86OpEntry opcodes_0F[256] = {
- [0x0E] = X86_OP_ENTRY0(EMMS, cpuid(3DNOW)),
/* femms */
- /*
- * 3DNow!'s opcode byte comes *after* modrm and displacements, making it
- * more like an Ib operand. Dispatch to the right helper in a single gen_*
- * function.
- */
- [0x0F] = X86_OP_ENTRY3(3dnow, P,q, Q,q, I,b, cpuid(3DNOW)),
-
[0x10] = X86_OP_GROUP0(0F10),
[0x11] = X86_OP_GROUP0(0F11),
[0x12] = X86_OP_GROUP0(0F12),
@@ -1086,8 +1078,54 @@ static const X86OpEntry opcodes_0F[256] = {
[0xa0] = X86_OP_ENTRYr(PUSH, FS, w),
[0xa1] = X86_OP_ENTRYw(POP, FS, w),
+ [0xb2] = X86_OP_ENTRY3(LSS, G,v, EM,p, None, None),
+ [0xb4] = X86_OP_ENTRY3(LFS, G,v, EM,p, None, None),
+ [0xb5] = X86_OP_ENTRY3(LGS, G,v, EM,p, None, None),
+ [0xb6] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, zextT0), /* MOVZX */
+ [0xb7] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, zextT0), /* MOVZX */
+
+ [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3
p_00_66_f3_f2),
+ [0xc3] = X86_OP_ENTRY3(MOV, EM,y,G,y, None,None, cpuid(SSE2)), /*
MOVNTI */
+ [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
+ [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
+ [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
+
+ [0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3)
p_66_f2),
+ [0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xd6] = X86_OP_GROUP0(0FD6),
+ [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256
p_00_66),
+
+ [0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
+ [0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
+ [0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xe6] = X86_OP_GROUP0(0FE6),
+ [0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66),
/* MOVNTQ/MOVNTDQ */
+
+ [0xf0] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex4_unal
cpuid(SSE3) p_f2), /* LDDQU */
+ [0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
+ [0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
+ [0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
+ [0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
+ [0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256
mmx p_00_66),
+
[0x0b] = X86_OP_ENTRY0(UD), /* UD2 */
[0x0d] = X86_OP_ENTRY1(NOP, M,v), /* 3DNow! prefetch */
+ [0x0e] = X86_OP_ENTRY0(EMMS, cpuid(3DNOW)),
/* femms */
+ /*
+ * 3DNow!'s opcode byte comes *after* modrm and displacements, making it
+ * more like an Ib operand. Dispatch to the right helper in a single gen_*
+ * function.
+ */
+ [0x0f] = X86_OP_ENTRY3(3dnow, P,q, Q,q, I,b, cpuid(3DNOW)),
[0x18] = X86_OP_ENTRY1(NOP, nop,v), /* prefetch/reserved NOP */
[0x19] = X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */
@@ -1169,23 +1207,11 @@ static const X86OpEntry opcodes_0F[256] = {
*/
[0xaf] = X86_OP_ENTRY3(IMUL3, G,v, E,v, 2op,v, sextT0),
- [0xb2] = X86_OP_ENTRY3(LSS, G,v, EM,p, None, None),
- [0xb4] = X86_OP_ENTRY3(LFS, G,v, EM,p, None, None),
- [0xb5] = X86_OP_ENTRY3(LGS, G,v, EM,p, None, None),
- [0xb6] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, zextT0), /* MOVZX */
- [0xb7] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, zextT0), /* MOVZX */
-
/* decoded as modrm, which is visible as a difference between page fault
and #UD */
[0xb9] = X86_OP_ENTRYr(UD, nop,v), /* UD1 */
[0xbe] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, sextT0), /* MOVSX */
[0xbf] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, sextT0), /* MOVSX */
- [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3
p_00_66_f3_f2),
- [0xc3] = X86_OP_ENTRY3(MOV, EM,y,G,y, None,None, cpuid(SSE2)), /*
MOVNTI */
- [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
- [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
- [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
-
[0xc8] = X86_OP_ENTRY1(BSWAP, LoBits,y),
[0xc9] = X86_OP_ENTRY1(BSWAP, LoBits,y),
[0xca] = X86_OP_ENTRY1(BSWAP, LoBits,y),
@@ -1195,33 +1221,6 @@ static const X86OpEntry opcodes_0F[256] = {
[0xce] = X86_OP_ENTRY1(BSWAP, LoBits,y),
[0xcf] = X86_OP_ENTRY1(BSWAP, LoBits,y),
- [0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3)
p_66_f2),
- [0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xd6] = X86_OP_GROUP0(0FD6),
- [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256
p_00_66),
-
- [0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
- [0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
- [0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xe6] = X86_OP_GROUP0(0FE6),
- [0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66),
/* MOVNTQ/MOVNTDQ */
-
- [0xf0] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex4_unal
cpuid(SSE3) p_f2), /* LDDQU */
- [0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
- [0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
- [0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256
p_00_66),
- [0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
- [0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256
mmx p_00_66),
-
/* Incorrectly missing from 2-17 */
[0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
[0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
--
2.45.1
- [PULL 07/25] target/i386: rewrite flags writeback for ADCX/ADOX, (continued)
- [PULL 07/25] target/i386: rewrite flags writeback for ADCX/ADOX, Paolo Bonzini, 2024/06/11
- [PULL 05/25] i386/sev: Return when sev_common is null, Paolo Bonzini, 2024/06/11
- [PULL 08/25] target/i386: put BLS* input in T1, use generic flag writeback, Paolo Bonzini, 2024/06/11
- [PULL 06/25] target/i386: remove CPUX86State argument from generator functions, Paolo Bonzini, 2024/06/11
- [PULL 09/25] target/i386: change X86_ENTRYr to use T0, Paolo Bonzini, 2024/06/11
- [PULL 10/25] target/i386: change X86_ENTRYwr to use T0, use it for moves, Paolo Bonzini, 2024/06/11
- [PULL 11/25] target/i386: replace NoSeg special with NoLoadEA, Paolo Bonzini, 2024/06/11
- [PULL 12/25] target/i386: fix processing of intercept 0 (read CR0), Paolo Bonzini, 2024/06/11
- [PULL 13/25] target/i386: convert MOV from/to CR and DR to new decoder, Paolo Bonzini, 2024/06/11
- [PULL 15/25] target/i386: finish converting 0F AE to the new decoder, Paolo Bonzini, 2024/06/11
- [PULL 14/25] target/i386: fix bad sorting of entries in the 0F table,
Paolo Bonzini <=
- [PULL 17/25] target/i386: split X86_CHECK_prot into PE and VM86 checks, Paolo Bonzini, 2024/06/11
- [PULL 16/25] target/i386: replace read_crN helper with read_cr8, Paolo Bonzini, 2024/06/11
- [PULL 18/25] target/i386: convert non-grouped, helper-based 2-byte opcodes, Paolo Bonzini, 2024/06/11
- [PULL 20/25] target/i386: adapt gen_shift_count for SHLD/SHRD, Paolo Bonzini, 2024/06/11
- [PULL 21/25] target/i386: convert SHLD/SHRD to new decoder, Paolo Bonzini, 2024/06/11
- [PULL 19/25] target/i386: pull load/writeback out of gen_shiftd_rm_T1, Paolo Bonzini, 2024/06/11
- [PULL 22/25] target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT to new decoder, Paolo Bonzini, 2024/06/11
- [PULL 23/25] target/i386: convert XADD to new decoder, Paolo Bonzini, 2024/06/11
- [PULL 24/25] target/i386: convert CMPXCHG to new decoder, Paolo Bonzini, 2024/06/11
- [PULL 25/25] target/i386: SEV: do not assume machine->cgs is SEV, Paolo Bonzini, 2024/06/11