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[PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable mode
From: |
Zhenzhong Duan |
Subject: |
[PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode |
Date: |
Mon, 30 Sep 2024 17:26:28 +0800 |
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48.
So default aw_bits to 48 in scalable modern mode. In other cases,
it is still default to 39 for backward compatibility.
Add a check to ensure user specified value is 48 in modern mode
for now.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
---
include/hw/i386/intel_iommu.h | 2 +-
hw/i386/intel_iommu.c | 10 +++++++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index b843d069cc..48134bda11 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -45,7 +45,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState,
INTEL_IOMMU_DEVICE)
#define DMAR_REG_SIZE 0x230
#define VTD_HOST_AW_39BIT 39
#define VTD_HOST_AW_48BIT 48
-#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
+#define VTD_HOST_AW_AUTO 0xff
#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
#define DMAR_REPORT_F_INTR (1)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 91d7b1abfa..068a08f522 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3776,7 +3776,7 @@ static Property vtd_properties[] = {
ON_OFF_AUTO_AUTO),
DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
- VTD_HOST_ADDRESS_WIDTH),
+ VTD_HOST_AW_AUTO),
DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
@@ -4683,6 +4683,14 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error
**errp)
}
}
+ if (s->aw_bits == VTD_HOST_AW_AUTO) {
+ if (s->scalable_modern) {
+ s->aw_bits = VTD_HOST_AW_48BIT;
+ } else {
+ s->aw_bits = VTD_HOST_AW_39BIT;
+ }
+ }
+
if (!s->scalable_modern && s->aw_bits != VTD_HOST_AW_39BIT &&
s->aw_bits != VTD_HOST_AW_48BIT) {
error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d",
--
2.34.1
- [PATCH v4 05/17] intel_iommu: Rename slpte to pte, (continued)
- [PATCH v4 05/17] intel_iommu: Rename slpte to pte, Zhenzhong Duan, 2024/09/30
- [PATCH v4 06/17] intel_iommu: Implement stage-1 translation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 07/17] intel_iommu: Check if the input address is canonical, Zhenzhong Duan, 2024/09/30
- [PATCH v4 08/17] intel_iommu: Set accessed and dirty bits during first stage translation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID, Zhenzhong Duan, 2024/09/30
- [PATCH v4 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap, Zhenzhong Duan, 2024/09/30
- [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode, Zhenzhong Duan, 2024/09/30
- [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode,
Zhenzhong Duan <=
- [PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting, Zhenzhong Duan, 2024/09/30
- [PATCH v4 17/17] tests/qtest: Add intel-iommu test, Zhenzhong Duan, 2024/09/30