Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores.
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 67 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 62115375cd..6547642287 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -49,6 +49,7 @@
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
+#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..8447ad0dfb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -579,6 +579,72 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
#endif
}
+/* Tenstorrent Ascalon */
+static void rv64_tt_ascalon_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV);
+ env->priv_ver = PRIV_VERSION_1_13_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.mmu = true;
+ cpu->cfg.vlenb = 256 >> 3;
+ cpu->cfg.elen = 64;
+ cpu->env.vext_ver = VEXT_VERSION_1_00_0;
+ cpu->cfg.rvv_ma_all_1s = true;
+ cpu->cfg.rvv_ta_all_1s = true;
+ cpu->cfg.misa_w = true;
+ cpu->cfg.pmp = true;
+ cpu->cfg.cbom_blocksize = 64;
+ cpu->cfg.cbop_blocksize = 64;
+ cpu->cfg.cboz_blocksize = 64;
+ cpu->cfg.ext_zic64b = true;
+ cpu->cfg.ext_zicbom = true;
+ cpu->cfg.ext_zicbop = true;
+ cpu->cfg.ext_zicboz = true;
+ cpu->cfg.ext_zicntr = true;
+ cpu->cfg.ext_zicond = true;
+ cpu->cfg.ext_zicsr = true;
+ cpu->cfg.ext_zifencei = true;
+ cpu->cfg.ext_zihintntl = true;
+ cpu->cfg.ext_zihintpause = true;
+ cpu->cfg.ext_zihpm = true;
+ cpu->cfg.ext_zimop = true;
+ cpu->cfg.ext_zawrs = true;
+ cpu->cfg.ext_zfa = true;
+ cpu->cfg.ext_zfbfmin = true;
+ cpu->cfg.ext_zfh = true;
+ cpu->cfg.ext_zfhmin = true;
+ cpu->cfg.ext_zcb = true;
+ cpu->cfg.ext_zcmop = true;
+ cpu->cfg.ext_zba = true;
+ cpu->cfg.ext_zbb = true;
+ cpu->cfg.ext_zbs = true;
+ cpu->cfg.ext_zkt = true;
+ cpu->cfg.ext_zvbb = true;
+ cpu->cfg.ext_zvbc = true;
+ cpu->cfg.ext_zvfbfmin = true;
+ cpu->cfg.ext_zvfbfwma = true;
+ cpu->cfg.ext_zvfh = true;
+ cpu->cfg.ext_zvfhmin = true;
+ cpu->cfg.ext_zvkng = true;
+ cpu->cfg.ext_smaia = true;
+ cpu->cfg.ext_smstateen = true;
+ cpu->cfg.ext_ssaia = true;
+ cpu->cfg.ext_sscofpmf = true;
+ cpu->cfg.ext_sstc = true;
+ cpu->cfg.ext_svade = true;
+ cpu->cfg.ext_svinval = true;
+ cpu->cfg.ext_svnapot = true;
+ cpu->cfg.ext_svpbmt = true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV57);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -2982,6 +3048,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,
rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64,
rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,
rv64_thead_c906_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,
rv64_tt_ascalon_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
rv64_veyron_v1_cpu_init),