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RE: [RFC PATCH 5/5] hw/arm/virt-acpi-build: Add IORT RMR regions to hand


From: Shameerali Kolothum Thodi
Subject: RE: [RFC PATCH 5/5] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding
Date: Thu, 14 Nov 2024 08:48:29 +0000

> -----Original Message-----
> From: Nicolin Chen <nicolinc@nvidia.com>
> Sent: Wednesday, November 13, 2024 6:31 PM
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org;
> eric.auger@redhat.com; peter.maydell@linaro.org; jgg@nvidia.com;
> ddutile@redhat.com; Linuxarm <linuxarm@huawei.com>; Wangzhou (B)
> <wangzhou1@hisilicon.com>; jiangkunkun <jiangkunkun@huawei.com>;
> Jonathan Cameron <jonathan.cameron@huawei.com>;
> zhangfei.gao@linaro.org
> Subject: Re: [RFC PATCH 5/5] hw/arm/virt-acpi-build: Add IORT RMR regions
> to handle MSI nested binding
> 
> On Fri, Nov 08, 2024 at 12:52:42PM +0000, Shameer Kolothum wrote:
> > From: Eric Auger <eric.auger@redhat.com>
> >
> > To handle SMMUv3 nested stage support it is practical to expose the
> > guest with reserved memory regions (RMRs) covering the IOVAs used by
> > the host kernel to map physical MSI doorbells.
> 
> There has been an ongoing solution for MSI alternative:
> https://lore.kernel.org/kvm/cover.1731130093.git.nicolinc@nvidia.com/
> 
> So, I think we should keep this patch out of this series, instead put it on 
> top
> of the testing branch.

Yes. I think then we can support DT solution as well. 

On that MSI RFC above, have you seen Eric's earlier/initial proposal to bind 
the Guest MSI in
nested cases. IIRC, it was providing an IOCTL and then creating a mapping in 
the host.

I think this is the latest on that.
https://lore.kernel.org/linux-iommu/20210411114659.15051-4-eric.auger@redhat.com/

But not sure, why we then moved to RMR approach. Eric?

Thanks,
Shameer



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