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[PATCH RESEND v2 01/19] hw/microblaze: Restrict MemoryRegionOps are impl
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH RESEND v2 01/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit |
Date: |
Thu, 14 Nov 2024 21:59:52 +0100 |
All these MemoryRegionOps read() and write() handlers are
implemented expecting 32-bit accesses. Clarify that setting
.impl.min/max_access_size fields.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
---
hw/char/xilinx_uartlite.c | 4 ++++
hw/intc/xilinx_intc.c | 4 ++++
hw/net/xilinx_ethlite.c | 4 ++++
hw/timer/xilinx_timer.c | 4 ++++
4 files changed, 16 insertions(+)
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
index f325084f8b..3022b3d8ef 100644
--- a/hw/char/xilinx_uartlite.c
+++ b/hw/char/xilinx_uartlite.c
@@ -170,6 +170,10 @@ static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 1,
.max_access_size = 4
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 6e5012e66e..8fb6b4f1a5 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -144,6 +144,10 @@ static const MemoryRegionOps pic_ops = {
.read = pic_read,
.write = pic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index bd81290808..e84b4cdd35 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -170,6 +170,10 @@ static const MemoryRegionOps eth_ops = {
.read = eth_read,
.write = eth_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 32a9df69e0..383fc8b3c8 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -193,6 +193,10 @@ static const MemoryRegionOps timer_ops = {
.read = timer_read,
.write = timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 4,
.max_access_size = 4
--
2.45.2
- [PATCH RESEND v2 00/19] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 01/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit,
Philippe Mathieu-Daudé <=
- [PATCH RESEND v2 02/19] hw/net/xilinx_ethlite: Convert some debug logs to trace events, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 03/19] hw/net/xilinx_ethlite: Remove unuseful debug logs, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 04/19] hw/net/xilinx_ethlite: Update QOM style, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 05/19] hw/net/xilinx_ethlite: Correct maximum RX buffer size, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 08/19] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 06/19] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented), Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 10/19] hw/net/xilinx_ethlite: Access TX_GIE register for each port, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 07/19] hw/net/xilinx_ethlite: Rename rxbuf -> port_index, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 09/19] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper, Philippe Mathieu-Daudé, 2024/11/14
- [PATCH RESEND v2 11/19] hw/net/xilinx_ethlite: Access TX_LEN register for each port, Philippe Mathieu-Daudé, 2024/11/14