Re: [PATCH for-10.0 1/7] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()

[Alistair Francis]

On Wed, Nov 6, 2024 at 11:38 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Move all the static initializion of the device to an init() function,
> leaving only the dynamic initialization to be done during realize.
>
> With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
> init(), and realize() will increment s->cap with the extra caps.
>
> This will allow callers to add IOMMU capabilities before the
> realization.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/riscv-iommu.c | 71 +++++++++++++++++++++++-------------------
>  1 file changed, 39 insertions(+), 32 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index feb650549a..1893584028 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -2096,11 +2096,48 @@ static const MemoryRegionOps riscv_iommu_trap_ops = {
>      }
>  };
>
> +static void riscv_iommu_instance_init(Object *obj)
> +{
> +    RISCVIOMMUState *s = RISCV_IOMMU(obj);
> +
> +    /* Enable translation debug interface */
> +    s->cap = RISCV_IOMMU_CAP_DBG;
> +
> +    /* Report QEMU target physical address space limits */
> +    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
> +                       TARGET_PHYS_ADDR_SPACE_BITS);
> +
> +    /* TODO: method to report supported PID bits */
> +    s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
> +    s->cap |= RISCV_IOMMU_CAP_PD8;
> +
> +    /* register storage */
> +    s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
> +    s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
> +    s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
> +
> +     /* Mark all registers read-only */
> +    memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
> +
> +    /* Device translation context cache */
> +    s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
> +                                         riscv_iommu_ctx_equal,
> +                                         g_free, NULL);
> +
> +    s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
> +                                         riscv_iommu_iot_equal,
> +                                         g_free, NULL);
> +
> +    s->iommus.le_next = NULL;
> +    s->iommus.le_prev = NULL;
> +    QLIST_INIT(&s->spaces);
> +}
> +
>  static void riscv_iommu_realize(DeviceState *dev, Error **errp)
>  {
>      RISCVIOMMUState *s = RISCV_IOMMU(dev);
>
> -    s->cap = s->version & RISCV_IOMMU_CAP_VERSION;
> +    s->cap |= s->version & RISCV_IOMMU_CAP_VERSION;
>      if (s->enable_msi) {
>          s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF;
>      }
> @@ -2115,29 +2152,11 @@ static void riscv_iommu_realize(DeviceState *dev, 
> Error **errp)
>          s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 |
>                    RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
>      }
> -    /* Enable translation debug interface */
> -    s->cap |= RISCV_IOMMU_CAP_DBG;
> -
> -    /* Report QEMU target physical address space limits */
> -    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
> -                       TARGET_PHYS_ADDR_SPACE_BITS);
> -
> -    /* TODO: method to report supported PID bits */
> -    s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
> -    s->cap |= RISCV_IOMMU_CAP_PD8;
>
>      /* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) 
> */
>      s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ?
>                          RISCV_IOMMU_DDTP_MODE_OFF : 
> RISCV_IOMMU_DDTP_MODE_BARE);
>
> -    /* register storage */
> -    s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
> -    s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
> -    s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
> -
> -     /* Mark all registers read-only */
> -    memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
> -
>      /*
>       * Register complete MMIO space, including MSI/PBA registers.
>       * Note, PCIDevice implementation will add overlapping MR for MSI/PBA,
> @@ -2195,19 +2214,6 @@ static void riscv_iommu_realize(DeviceState *dev, 
> Error **errp)
>      memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops, s,
>              "riscv-iommu-trap", ~0ULL);
>      address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as");
> -
> -    /* Device translation context cache */
> -    s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
> -                                         riscv_iommu_ctx_equal,
> -                                         g_free, NULL);
> -
> -    s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
> -                                         riscv_iommu_iot_equal,
> -                                         g_free, NULL);
> -
> -    s->iommus.le_next = NULL;
> -    s->iommus.le_prev = NULL;
> -    QLIST_INIT(&s->spaces);
>  }
>
>  static void riscv_iommu_unrealize(DeviceState *dev)
> @@ -2249,6 +2255,7 @@ static const TypeInfo riscv_iommu_info = {
>      .name = TYPE_RISCV_IOMMU,
>      .parent = TYPE_DEVICE,
>      .instance_size = sizeof(RISCVIOMMUState),
> +    .instance_init = riscv_iommu_instance_init,
>      .class_init = riscv_iommu_class_init,
>  };
>
> --
> 2.45.2
>
>