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Re: [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names |
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Date: |
Mon, 25 Nov 2024 11:58:04 +0000 |
On Thu, 21 Nov 2024 at 17:16, Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> According to Cortex-R5 r1p2 manual, register with opcode2=0 is
> BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
> qemu labels them. Just swap the labels to avoid confusion, -
> both registers are implemented as always-zero.
>
> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
> ---
> target/arm/tcg/cpu32.c | 4 ++--
Applied to target-arm.next, thanks.
-- PMM