The RISC-V Server Platform specification[1] defines a standardized set
of hardware and software capabilities, that portable system software,
such as OS and hypervisors can rely on being present in a RISC-V server
platform. This patchset provides a RISC-V Server Platform (RVSP)
reference implementation on qemu which is in compliance with the spec
as faithful as possible.
The reference board can be running with tag edk2-stable202308 in
upstream edk2 repo[2].
The qemu command line used:
$QEMU -nographic -m 4G -smp 2 \
-machine rvsp-ref,pflash0=pflash0,pflash1=pflash1 \
-blockdev
node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \
-blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \
-bios fw_dynamic.bin \
-drive file=$BRS_IMG,if=ide,format=raw
Since there is no ACPI table generated in this new machine type, a
corresponding EDK-II platform (WIP) is needed to provide related ACPI
tables.
For testing purposes only, we used a workaround to generate the ACPI
tables in Qemu with a dedicated downstream patch.
[1] https://github.com/riscv-non-isa/riscv-server-platform
[2] https://github.com/tianocore/edk2.git
v2:
- move cpu definition the 1st patch
- replace sifive_test with power reset syscon
- add versioning scheme to fdt
- integrate recent changes in virt.c
- use g_autofree
- create_fdt/finalize_fdt
- riscv_isa_write_fdt
- some cleanups
Fei Wu (2):
target/riscv: Add server platform reference cpu
hw/riscv: Add server platform reference machine
configs/devices/riscv64-softmmu/default.mak | 1 +
hw/riscv/Kconfig | 12 +
hw/riscv/meson.build | 1 +
hw/riscv/server_platform_ref.c | 1276 +++++++++++++++++++
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 61 +
6 files changed, 1352 insertions(+)
create mode 100644 hw/riscv/server_platform_ref.c