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[PATCH 00/13] target/mips: Simplify some target_ulong registers to 32-bi
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 00/13] target/mips: Simplify some target_ulong registers to 32-bit |
Date: |
Tue, 26 Nov 2024 14:15:32 +0100 |
This series is part of an experiment trying to run 32/64-bit
MIPS cores in the same process.
MXU is only available for 32-bit ISA, so there we have
target_ulong == uint32_t.
DSPControl is a 32-bit register, so we can also use uint32_t.
First introduce 32-bit equivalent helper_i32() for some MIPS
specific helper_tl(), then use them in mxu_translate.c, using
32-bit registers.
For DSPControl register, we convert it to 32-bit, and use
truncate() when using a 64-bit argument, or extu() when
returning to 64-bit.
Philippe Mathieu-Daudé (13):
target/mips: Rename gen_load_gpr() -> gen_load_gpr_tl()
target/mips: Rename gen_store_gpr() -> gen_store_gpr_tl()
target/mips: Rename gen_move_low32() -> gen_move_low32_tl()
target/mips: Rename gen_move_high32() -> gen_move_high32_tl()
target/mips: Rename gen_base_offset_addr() ->
gen_base_offset_addr_tl()
target/mips: Rename gen_op_addr_add?() -> gen_op_addr_add?_tl()
target/mips: Introduce gen_load_gpr_i32()
target/mips: Introduce gen_store_gpr_i32()
target/mips: Introduce gen_move_low32_i32()
target/mips: Introduce gen_move_high32_i32()
target/mips: Declare MXU registers as 32-bit
target/mips: Access MXU registers using TCGv_i32 API
target/mips: Make DSPControl register 32-bit wide
target/mips/cpu.h | 6 +-
target/mips/tcg/translate.h | 18 +-
target/mips/tcg/sysemu_helper.h.inc | 4 +-
target/mips/sysemu/machine.c | 9 +-
target/mips/tcg/dsp_helper.c | 10 +-
target/mips/tcg/lcsr_translate.c | 12 +-
target/mips/tcg/loong_translate.c | 20 +-
target/mips/tcg/msa_translate.c | 6 +-
target/mips/tcg/mxu_translate.c | 1546 ++++++++++-----------
target/mips/tcg/octeon_translate.c | 28 +-
target/mips/tcg/sysemu/cp0_helper.c | 4 +-
target/mips/tcg/translate.c | 520 +++----
target/mips/tcg/translate_addr_const.c | 8 +-
target/mips/tcg/tx79_translate.c | 36 +-
target/mips/tcg/vr54xx_translate.c | 6 +-
target/mips/tcg/micromips_translate.c.inc | 38 +-
target/mips/tcg/mips16e_translate.c.inc | 32 +-
target/mips/tcg/nanomips_translate.c.inc | 438 +++---
18 files changed, 1400 insertions(+), 1341 deletions(-)
--
2.45.2
- [PATCH 00/13] target/mips: Simplify some target_ulong registers to 32-bit,
Philippe Mathieu-Daudé <=
- [PATCH 01/13] target/mips: Rename gen_load_gpr() -> gen_load_gpr_tl(), Philippe Mathieu-Daudé, 2024/11/26
- [PATCH 02/13] target/mips: Rename gen_store_gpr() -> gen_store_gpr_tl(), Philippe Mathieu-Daudé, 2024/11/26
- [PATCH 04/13] target/mips: Rename gen_move_high32() -> gen_move_high32_tl(), Philippe Mathieu-Daudé, 2024/11/26
- [PATCH 03/13] target/mips: Rename gen_move_low32() -> gen_move_low32_tl(), Philippe Mathieu-Daudé, 2024/11/26
- [PATCH 05/13] target/mips: Rename gen_base_offset_addr() -> gen_base_offset_addr_tl(), Philippe Mathieu-Daudé, 2024/11/26