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Re: [PATCH for-9.2] target/riscv: Avoid bad shift in riscv_cpu_do_interr


From: Richard Henderson
Subject: Re: [PATCH for-9.2] target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
Date: Thu, 28 Nov 2024 06:58:50 -0600
User-agent: Mozilla Thunderbird

On 11/28/24 04:38, Peter Maydell wrote:
In riscv_cpu_do_interrupt() we use the 'cause' value we got out of
cs->exception as a shift value.  However this value can be larger
than 31, which means that "1 << cause" is undefined behaviour,
because we do the shift on an 'int' type.

This causes the undefined behaviour sanitizer to complain
on one of the check-tcg tests:

$ UBSAN_OPTIONS=print_stacktrace=1:abort_on_error=1:halt_on_error=1 
./build/clang/qemu-system-riscv64 -M virt -semihosting -display none -device 
loader,file=build/clang/tests/tcg/riscv64-softmmu/issue1060
../../target/riscv/cpu_helper.c:1805:38: runtime error: shift exponent 63 is 
too large for 32-bit type 'int'
     #0 0x55f2dc026703 in riscv_cpu_do_interrupt 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/clang/../../target/riscv/cpu_helper.c:1805:38
     #1 0x55f2dc3d170e in cpu_handle_exception 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/clang/../../accel/tcg/cpu-exec.c:752:9

In this case cause is RISCV_EXCP_SEMIHOST, which is 0x3f.

Semihosting is completely artificial and should never be injected.
The maximum "real" cause is

    RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,

We ought to hoist the handling of RISCV_EXCP_SEMIHOST higher in the function, before these calculations.


r~



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