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[PATCH v2 03/23] target/loongarch: Fix PGD CSR for LoongArch32
From: |
Jiaxun Yang |
Subject: |
[PATCH v2 03/23] target/loongarch: Fix PGD CSR for LoongArch32 |
Date: |
Thu, 26 Dec 2024 21:19:34 +0000 |
As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/loongarch/tcg/csr_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/tcg/csr_helper.c
b/target/loongarch/tcg/csr_helper.c
index
15f94caefabc7722263fa46e948e21de37b4203c..821aa6af46ea2129d771fdc937eca72317cefc1e
100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -26,7 +26,7 @@ target_ulong helper_csrrd_pgd(CPULoongArchState *env)
v = env->CSR_BADV;
}
- if ((v >> 63) & 0x1) {
+ if (extract64(v, is_la64(env) ? 63 : 31, 1)) {
v = env->CSR_PGDH;
} else {
v = env->CSR_PGDL;
--
2.43.0
- [PATCH v2 00/23] target/loongarch: LoongArch32 fixes 1, Jiaxun Yang, 2024/12/26
- [PATCH v2 01/23] target/loongarch: Enable rotr.w/rotri.w for LoongArch32, Jiaxun Yang, 2024/12/26
- [PATCH v2 02/23] target/loongarch: Fix address generation for gen_sc, Jiaxun Yang, 2024/12/26
- [PATCH v2 03/23] target/loongarch: Fix PGD CSR for LoongArch32,
Jiaxun Yang <=
- [PATCH v2 04/23] target/loongarch: Perform sign extension for IOCSR reads, Jiaxun Yang, 2024/12/26
- [PATCH v2 05/23] target/loongarch: Use target_ulong for iocsrrd helper results, Jiaxun Yang, 2024/12/26
- [PATCH v2 06/23] target/loongarch: Store some uint64_t values as target_ulong, Jiaxun Yang, 2024/12/26
- [PATCH v2 07/23] target/loongarch: Cast address to 64bit before DMW_64_VSEG shift, Jiaxun Yang, 2024/12/26