[PATCH RFC] target/riscv: Remove tbflag for VILL

[Ben Dooks]

Since the ctx->vill is only really applicable if the LMUL value is
set to an invalid state (4) we can free the tbflag up by just using
the LMUL field.

This was discussed in [1] as part of a way of extending the space in
tbflags to allow our big-endian work to have a bit in there.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

[1] https://mail.gnu.org/archive/html/qemu-devel/2025-04/msg03982.html
---
 target/riscv/cpu.h        | 2 +-
 target/riscv/cpu_helper.c | 7 +++++--
 target/riscv/translate.c  | 5 ++++-
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 167909c89b..2811d6d3f7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -635,7 +635,7 @@ FIELD(TB_FLAGS, VS, 5, 2)
 FIELD(TB_FLAGS, LMUL, 7, 3)
 FIELD(TB_FLAGS, SEW, 10, 3)
 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
-FIELD(TB_FLAGS, VILL, 14, 1)
+/* VILL replaced by checked of LMUL==4 */
 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 FIELD(TB_FLAGS, XL, 16, 2)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 619c76cc00..290ed7c30b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -38,6 +38,9 @@
 #include "debug.h"
 #include "pmp.h"
 
+/* avoid pulling in the tcg/riscv/tcg-target.c.inc */
+#define VLMUL_RESERVED (4)
+
 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
 {
 #ifdef CONFIG_USER_ONLY
@@ -164,7 +167,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
         uint32_t maxsz = vlmax << vsew;
         bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
                            (maxsz >= 8);
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
+        g_assert(env->vill && lmul != VLMUL_RESERVED);
         flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew);
         flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
                            FIELD_EX64(env->vtype, VTYPE, VLMUL));
@@ -175,7 +178,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
                            FIELD_EX64(env->vtype, VTYPE, VMA));
         flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
     } else {
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
+        flags = FIELD_DP32(flags, TB_FLAGS, LMUL, VLMUL_RESERVED);
     }
 
     if (cpu_get_fcfien(env)) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index cef61b5b29..28a6b345f2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -37,6 +37,9 @@
 
 #include "tcg/tcg-cpu.h"
 
+/* avoid pulling in the tcg/riscv/tcg-target.c.inc */
+#define VLMUL_RESERVED (4)
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -1274,9 +1277,9 @@ static void riscv_tr_init_disas_context(DisasContextBase 
*dcbase, CPUState *cs)
     ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->cfg_ptr = &(cpu->cfg);
-    ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
     ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
+    ctx->vill = ctx->lmul == VLMUL_RESERVED;
     ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
     ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
     ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
-- 
2.37.2.352.g3c44437643