RE: [PATCH v1 05/22] hw/misc/aspeed_hace: Introduce 64-bit digest_addr variable for AST2700

[Jamin Lin]

Hi Cédric

> Subject: Re: [PATCH v1 05/22] hw/misc/aspeed_hace: Introduce 64-bit
> digest_addr variable for AST2700
> 
> On 3/21/25 10:26, Jamin Lin wrote:
> > The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a
> > 64-bit DRAM address space. To support future AST2700 updates, a new
> "digest_addr"
> > variable is introduced with a 64-bit data type.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/misc/aspeed_hace.c | 4 +++-
> >   1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index
> > 9771d6e490..8cf3f194a5 100644
> > --- a/hw/misc/aspeed_hace.c
> > +++ b/hw/misc/aspeed_hace.c
> > @@ -148,6 +148,7 @@ static void do_hash_operation(AspeedHACEState *s,
> int algo, bool sg_mode,
> >       bool sg_acc_mode_final_request = false;
> >       g_autofree uint8_t *digest_buf = NULL;
> >       struct iovec iov[ASPEED_HACE_MAX_SG];
> > +    uint64_t digest_addr = 0;
> >       Error *local_err = NULL;
> >       uint32_t total_msg_len;
> >       size_t digest_len = 0;
> > @@ -257,7 +258,8 @@ static void do_hash_operation(AspeedHACEState *s,
> int algo, bool sg_mode,
> >           return;
> >       }
> >
> > -    if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST],
> > +    digest_addr = deposit64(digest_addr, 0, 32,
> > + s->regs[R_HASH_DEST]);
> 
> As on the previous patch, an helper would be useful and is there an alignment
> constraint ?
> 
Thanks for the review and suggestion.
I will add the hash_get_digest_addr helper function to retrieve the hash digest 
address.
The digest address must be 8-byte aligned.
To enforce this, we already define a "dest_mask" class attribute and set it to 
0x7FFFFFF8, which ensures proper 8-byte alignment of digest_addr.

Reference
https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_hace.c#L365
case R_HASH_DEST:
        data &= ahc->dest_mask;
https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_hace.c#L584
    ahc->dest_mask = 0x7FFFFFF8;

For more details, please refer to the Hash & Crypto Engine section(HACE24) in 
the datasheet.
Thanks-Jamin

> 
> Thanks,
> 
> C.
> 
> 
> 
> > +    if (address_space_write(&s->dram_as, digest_addr,
> >                               MEMTXATTRS_UNSPECIFIED,
> >                               digest_buf, digest_len)) {
> >           qemu_log_mask(LOG_GUEST_ERROR,