Re: [PATCH v4 20/27] target/i386/cpu: Remove CPUX86State::enable_l3_cache field

[Zhao Liu]

On Thu, May 08, 2025 at 03:35:43PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu,  8 May 2025 15:35:43 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v4 20/27] target/i386/cpu: Remove
>  CPUX86State::enable_l3_cache field
> X-Mailer: git-send-email 2.47.1
> 
> The CPUX86State::enable_l3_cache boolean was only disabled
> for the pc-q35-2.7 and pc-i440fx-2.7 machines, which got
> removed.  Being now always %true, we can remove it and simplify
> cpu_x86_cpuid() and encode_cache_cpuid80000006().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/i386/cpu.h |  6 ------
>  target/i386/cpu.c | 39 +++++++++++++--------------------------
>  2 files changed, 13 insertions(+), 32 deletions(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index b5cbd91c156..62239b0a562 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2219,12 +2219,6 @@ struct ArchCPU {
>       */
>      bool enable_lmce;
>  
> -    /* Compatibility bits for old machine types.
> -     * If true present virtual l3 cache for VM, the vcpus in the same virtual
> -     * socket share an virtual l3 cache.
> -     */
> -    bool enable_l3_cache;
> -
>      /* Compatibility bits for old machine types.
>       * If true present L1 cache as per-thread, not per-core.
>       */

I realize this is another special case.

There is no support for hybrid x86 CPUs in QEMU, but it's also true that
there are some actual modern x86 Client CPUs without l3 cache, such as
Intel MTL's low power E core (and it has vmx support, i.e., support KVM).

So I think we can keep this property as well, to have some more
configuration options for users' emulation.